/* SPDX-License-Identifier: GPL-2.0-only * Copyright (C) 2020 Marvell. */ #ifndef __OTX2_CPT_HW_TYPES_H #define __OTX2_CPT_HW_TYPES_H #include <linux/types.h> /* Device IDs */ #define OTX2_CPT_PCI_PF_DEVICE_ID … #define OTX2_CPT_PCI_VF_DEVICE_ID … #define CN10K_CPT_PCI_PF_DEVICE_ID … #define CN10K_CPT_PCI_VF_DEVICE_ID … #define CPT_PCI_SUBSYS_DEVID_CN10K_A … #define CPT_PCI_SUBSYS_DEVID_CN10K_B … /* Mailbox interrupts offset */ #define OTX2_CPT_PF_MBOX_INT … #define OTX2_CPT_PF_INT_VEC_E_MBOXX(x, a) … /* Maximum supported microcode groups */ #define OTX2_CPT_MAX_ENGINE_GROUPS … /* CPT instruction size in bytes */ #define OTX2_CPT_INST_SIZE … /* * CPT VF MSIX vectors and their offsets */ #define OTX2_CPT_VF_MSIX_VECTORS … #define OTX2_CPT_VF_INTR_MBOX_MASK … #define CN10K_CPT_VF_MBOX_REGION … /* CPT LF MSIX vectors */ #define OTX2_CPT_LF_MSIX_VECTORS … /* OcteonTX2 CPT PF registers */ #define OTX2_CPT_PF_CONSTANTS … #define OTX2_CPT_PF_RESET … #define OTX2_CPT_PF_DIAG … #define OTX2_CPT_PF_BIST_STATUS … #define OTX2_CPT_PF_ECC0_CTL … #define OTX2_CPT_PF_ECC0_FLIP … #define OTX2_CPT_PF_ECC0_INT … #define OTX2_CPT_PF_ECC0_INT_W1S … #define OTX2_CPT_PF_ECC0_ENA_W1S … #define OTX2_CPT_PF_ECC0_ENA_W1C … #define OTX2_CPT_PF_MBOX_INTX(b) … #define OTX2_CPT_PF_MBOX_INT_W1SX(b) … #define OTX2_CPT_PF_MBOX_ENA_W1CX(b) … #define OTX2_CPT_PF_MBOX_ENA_W1SX(b) … #define OTX2_CPT_PF_EXEC_INT … #define OTX2_CPT_PF_EXEC_INT_W1S … #define OTX2_CPT_PF_EXEC_ENA_W1C … #define OTX2_CPT_PF_EXEC_ENA_W1S … #define OTX2_CPT_PF_GX_EN(b) … #define OTX2_CPT_PF_EXEC_INFO … #define OTX2_CPT_PF_EXEC_BUSY … #define OTX2_CPT_PF_EXEC_INFO0 … #define OTX2_CPT_PF_EXEC_INFO1 … #define OTX2_CPT_PF_INST_REQ_PC … #define OTX2_CPT_PF_INST_LATENCY_PC … #define OTX2_CPT_PF_RD_REQ_PC … #define OTX2_CPT_PF_RD_LATENCY_PC … #define OTX2_CPT_PF_RD_UC_PC … #define OTX2_CPT_PF_ACTIVE_CYCLES_PC … #define OTX2_CPT_PF_EXE_CTL … #define OTX2_CPT_PF_EXE_STATUS … #define OTX2_CPT_PF_EXE_CLK … #define OTX2_CPT_PF_EXE_DBG_CTL … #define OTX2_CPT_PF_EXE_DBG_DATA … #define OTX2_CPT_PF_EXE_BIST_STATUS … #define OTX2_CPT_PF_EXE_REQ_TIMER … #define OTX2_CPT_PF_EXE_MEM_CTL … #define OTX2_CPT_PF_EXE_PERF_CTL … #define OTX2_CPT_PF_EXE_DBG_CNTX(b) … #define OTX2_CPT_PF_EXE_PERF_EVENT_CNT … #define OTX2_CPT_PF_EXE_EPCI_INBX_CNT(b) … #define OTX2_CPT_PF_EXE_EPCI_OUTBX_CNT(b) … #define OTX2_CPT_PF_ENGX_UCODE_BASE(b) … #define OTX2_CPT_PF_QX_CTL(b) … #define OTX2_CPT_PF_QX_GMCTL(b) … #define OTX2_CPT_PF_QX_CTL2(b) … #define OTX2_CPT_PF_VFX_MBOXX(b, c) … /* OcteonTX2 CPT LF registers */ #define OTX2_CPT_LF_CTL … #define OTX2_CPT_LF_DONE_WAIT … #define OTX2_CPT_LF_INPROG … #define OTX2_CPT_LF_DONE … #define OTX2_CPT_LF_DONE_ACK … #define OTX2_CPT_LF_DONE_INT_ENA_W1S … #define OTX2_CPT_LF_DONE_INT_ENA_W1C … #define OTX2_CPT_LF_MISC_INT … #define OTX2_CPT_LF_MISC_INT_W1S … #define OTX2_CPT_LF_MISC_INT_ENA_W1S … #define OTX2_CPT_LF_MISC_INT_ENA_W1C … #define OTX2_CPT_LF_Q_BASE … #define OTX2_CPT_LF_Q_SIZE … #define OTX2_CPT_LF_Q_INST_PTR … #define OTX2_CPT_LF_Q_GRP_PTR … #define OTX2_CPT_LF_NQX(a) … #define OTX2_CPT_LF_CTX_CTL … #define OTX2_CPT_LF_CTX_FLUSH … #define OTX2_CPT_LF_CTX_ERR … #define OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT … /* LMT LF registers */ #define OTX2_CPT_LMT_LFBASE … #define OTX2_CPT_LMT_LF_LMTLINEX(a) … /* RVU VF registers */ #define OTX2_RVU_VF_INT … #define OTX2_RVU_VF_INT_W1S … #define OTX2_RVU_VF_INT_ENA_W1S … #define OTX2_RVU_VF_INT_ENA_W1C … /* * Enumeration otx2_cpt_ucode_error_code_e * * Enumerates ucode errors */ enum otx2_cpt_ucode_comp_code_e { … }; /* * Enumeration otx2_cpt_comp_e * * OcteonTX2 CPT Completion Enumeration * Enumerates the values of CPT_RES_S[COMPCODE]. */ enum otx2_cpt_comp_e { … }; /* * Enumeration otx2_cpt_vf_int_vec_e * * OcteonTX2 CPT VF MSI-X Vector Enumeration * Enumerates the MSI-X interrupt vectors. */ enum otx2_cpt_vf_int_vec_e { … }; /* * Enumeration otx2_cpt_lf_int_vec_e * * OcteonTX2 CPT LF MSI-X Vector Enumeration * Enumerates the MSI-X interrupt vectors. */ enum otx2_cpt_lf_int_vec_e { … }; /* * Structure otx2_cpt_inst_s * * CPT Instruction Structure * This structure specifies the instruction layout. Instructions are * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set. * cpt_inst_s_s * Word 0 * doneint:1 Done interrupt. * 0 = No interrupts related to this instruction. * 1 = When the instruction completes, CPT()_VQ()_DONE[DONE] will be * incremented,and based on the rules described there an interrupt may * occur. * Word 1 * res_addr [127: 64] Result IOVA. * If nonzero, specifies where to write CPT_RES_S. * If zero, no result structure will be written. * Address must be 16-byte aligned. * Bits <63:49> are ignored by hardware; software should use a * sign-extended bit <48> for forward compatibility. * Word 2 * grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when * CPT submits work SSO. * For the SSO to not discard the add-work request, FPA_PF_MAP() must map * [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid. * tt:2 [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use when CPT * submits work to SSO * tag:32 [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when CPT * submits work to SSO. * Word 3 * wq_ptr [255:192] If [WQ_PTR] is nonzero, it is a pointer to a * work-queue entry that CPT submits work to SSO after all context, * output data, and result write operations are visible to other * CNXXXX units and the cores. Bits <2:0> must be zero. * Bits <63:49> are ignored by hardware; software should * use a sign-extended bit <48> for forward compatibility. * Internal: * Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0. * Word 4 * ei0; [319:256] Engine instruction word 0. Passed to the AE/SE. * Word 5 * ei1; [383:320] Engine instruction word 1. Passed to the AE/SE. * Word 6 * ei2; [447:384] Engine instruction word 1. Passed to the AE/SE. * Word 7 * ei3; [511:448] Engine instruction word 1. Passed to the AE/SE. * */ otx2_cpt_inst_s; /* * Structure otx2_cpt_res_s * * CPT Result Structure * The CPT coprocessor writes the result structure after it completes a * CPT_INST_S instruction. The result structure is exactly 16 bytes, and * each instruction completion produces exactly one result structure. * * This structure is stored in memory as little-endian unless * CPT()_PF_Q()_CTL[INST_BE] is set. * cpt_res_s_s * Word 0 * doneint:1 [16:16] Done interrupt. This bit is copied from the * corresponding instruction's CPT_INST_S[DONEINT]. * compcode:8 [7:0] Indicates completion/error status of the CPT coprocessor * for the associated instruction, as enumerated by CPT_COMP_E. * Core software may write the memory location containing [COMPCODE] to * 0x0 before ringing the doorbell, and then poll for completion by * checking for a nonzero value. * Once the core observes a nonzero [COMPCODE] value in this case,the CPT * coprocessor will have also completed L2/DRAM write operations. * Word 1 * reserved * */ otx2_cpt_res_s; /* * Register (RVU_PF_BAR0) cpt#_af_constants1 * * CPT AF Constants Register * This register contains implementation-related parameters of CPT. */ otx2_cptx_af_constants1; /* * RVU_PFVF_BAR2 - cpt_lf_misc_int * * This register contain the per-queue miscellaneous interrupts. * */ otx2_cptx_lf_misc_int; /* * RVU_PFVF_BAR2 - cpt_lf_misc_int_ena_w1s * * This register sets interrupt enable bits. * */ otx2_cptx_lf_misc_int_ena_w1s; /* * RVU_PFVF_BAR2 - cpt_lf_ctl * * This register configures the queue. * * When the queue is not execution-quiescent (see CPT_LF_INPROG[EENA,INFLIGHT]), * software must only write this register with [ENA]=0. */ otx2_cptx_lf_ctl; /* * RVU_PFVF_BAR2 - cpt_lf_done_wait * * This register specifies the per-queue interrupt coalescing settings. */ otx2_cptx_lf_done_wait; /* * RVU_PFVF_BAR2 - cpt_lf_done * * This register contain the per-queue instruction done count. */ otx2_cptx_lf_done; /* * RVU_PFVF_BAR2 - cpt_lf_inprog * * These registers contain the per-queue instruction in flight registers. * */ otx2_cptx_lf_inprog; /* * RVU_PFVF_BAR2 - cpt_lf_q_base * * CPT initializes these CSR fields to these values on any CPT_LF_Q_BASE write: * _ CPT_LF_Q_INST_PTR[XQ_XOR]=0. * _ CPT_LF_Q_INST_PTR[NQ_PTR]=2. * _ CPT_LF_Q_INST_PTR[DQ_PTR]=2. * _ CPT_LF_Q_GRP_PTR[XQ_XOR]=0. * _ CPT_LF_Q_GRP_PTR[NQ_PTR]=1. * _ CPT_LF_Q_GRP_PTR[DQ_PTR]=1. */ otx2_cptx_lf_q_base; /* * RVU_PFVF_BAR2 - cpt_lf_q_size * * CPT initializes these CSR fields to these values on any CPT_LF_Q_SIZE write: * _ CPT_LF_Q_INST_PTR[XQ_XOR]=0. * _ CPT_LF_Q_INST_PTR[NQ_PTR]=2. * _ CPT_LF_Q_INST_PTR[DQ_PTR]=2. * _ CPT_LF_Q_GRP_PTR[XQ_XOR]=0. * _ CPT_LF_Q_GRP_PTR[NQ_PTR]=1. * _ CPT_LF_Q_GRP_PTR[DQ_PTR]=1. */ otx2_cptx_lf_q_size; /* * RVU_PF_BAR0 - cpt_af_lf_ctl * * This register configures queues. This register should be written only * when the queue is execution-quiescent (see CPT_LF_INPROG[INFLIGHT]). */ otx2_cptx_af_lf_ctrl; #endif /* __OTX2_CPT_HW_TYPES_H */
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