// SPDX-License-Identifier: GPL-2.0-only /* Copyright (C) 2020 Marvell. */ #include <linux/ctype.h> #include <linux/firmware.h> #include "otx2_cptpf_ucode.h" #include "otx2_cpt_common.h" #include "otx2_cptpf.h" #include "otx2_cptlf.h" #include "otx2_cpt_reqmgr.h" #include "rvu_reg.h" #define CSR_DELAY … #define LOADFVC_RLEN … #define LOADFVC_MAJOR_OP … #define LOADFVC_MINOR_OP … /* * Interval to flush dirty data for next CTX entry. The interval is measured * in increments of 10ns(interval time = CTX_FLUSH_TIMER_COUNT * 10ns). */ #define CTX_FLUSH_TIMER_CNT … struct fw_info_t { … }; static struct otx2_cpt_bitmap get_cores_bmap(struct device *dev, struct otx2_cpt_eng_grp_info *eng_grp) { … } static int is_eng_type(int val, int eng_type) { … } static int is_2nd_ucode_used(struct otx2_cpt_eng_grp_info *eng_grp) { … } static void set_ucode_filename(struct otx2_cpt_ucode *ucode, const char *filename) { … } static char *get_eng_type_str(int eng_type) { … } static char *get_ucode_type_str(int ucode_type) { … } static int get_ucode_type(struct device *dev, struct otx2_cpt_ucode_hdr *ucode_hdr, int *ucode_type, u16 rid) { … } static int __write_ucode_base(struct otx2_cptpf_dev *cptpf, int eng, dma_addr_t dma_addr, int blkaddr) { … } static int cptx_set_ucode_base(struct otx2_cpt_eng_grp_info *eng_grp, struct otx2_cptpf_dev *cptpf, int blkaddr) { … } static int cpt_set_ucode_base(struct otx2_cpt_eng_grp_info *eng_grp, void *obj) { … } static int cptx_detach_and_disable_cores(struct otx2_cpt_eng_grp_info *eng_grp, struct otx2_cptpf_dev *cptpf, struct otx2_cpt_bitmap bmap, int blkaddr) { … } static int cpt_detach_and_disable_cores(struct otx2_cpt_eng_grp_info *eng_grp, void *obj) { … } static int cptx_attach_and_enable_cores(struct otx2_cpt_eng_grp_info *eng_grp, struct otx2_cptpf_dev *cptpf, struct otx2_cpt_bitmap bmap, int blkaddr) { … } static int cpt_attach_and_enable_cores(struct otx2_cpt_eng_grp_info *eng_grp, void *obj) { … } static int load_fw(struct device *dev, struct fw_info_t *fw_info, char *filename, u16 rid) { … } static void cpt_ucode_release_fw(struct fw_info_t *fw_info) { … } static struct otx2_cpt_uc_info_t *get_ucode(struct fw_info_t *fw_info, int ucode_type) { … } static void print_uc_info(struct fw_info_t *fw_info) { … } static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t *fw_info, u16 rid) { … } struct otx2_cpt_engs_rsvd *find_engines_by_type( struct otx2_cpt_eng_grp_info *eng_grp, int eng_type) { … } static int eng_grp_has_eng_type(struct otx2_cpt_eng_grp_info *eng_grp, int eng_type) { … } static int update_engines_avail_count(struct device *dev, struct otx2_cpt_engs_available *avail, struct otx2_cpt_engs_rsvd *engs, int val) { … } static int update_engines_offset(struct device *dev, struct otx2_cpt_engs_available *avail, struct otx2_cpt_engs_rsvd *engs) { … } static int release_engines(struct device *dev, struct otx2_cpt_eng_grp_info *grp) { … } static int do_reserve_engines(struct device *dev, struct otx2_cpt_eng_grp_info *grp, struct otx2_cpt_engines *req_engs) { … } static int check_engines_availability(struct device *dev, struct otx2_cpt_eng_grp_info *grp, struct otx2_cpt_engines *req_eng) { … } static int reserve_engines(struct device *dev, struct otx2_cpt_eng_grp_info *grp, struct otx2_cpt_engines *req_engs, int ucodes_cnt) { … } static void ucode_unload(struct device *dev, struct otx2_cpt_ucode *ucode) { … } static int copy_ucode_to_dma_mem(struct device *dev, struct otx2_cpt_ucode *ucode, const u8 *ucode_data) { … } static int enable_eng_grp(struct otx2_cpt_eng_grp_info *eng_grp, void *obj) { … } static int disable_eng_grp(struct device *dev, struct otx2_cpt_eng_grp_info *eng_grp, void *obj) { … } static void setup_eng_grp_mirroring(struct otx2_cpt_eng_grp_info *dst_grp, struct otx2_cpt_eng_grp_info *src_grp) { … } static void remove_eng_grp_mirroring(struct otx2_cpt_eng_grp_info *dst_grp) { … } static void update_requested_engs(struct otx2_cpt_eng_grp_info *mirror_eng_grp, struct otx2_cpt_engines *engs, int engs_cnt) { … } static struct otx2_cpt_eng_grp_info *find_mirrored_eng_grp( struct otx2_cpt_eng_grp_info *grp) { … } static struct otx2_cpt_eng_grp_info *find_unused_eng_grp( struct otx2_cpt_eng_grps *eng_grps) { … } static int eng_grp_update_masks(struct device *dev, struct otx2_cpt_eng_grp_info *eng_grp) { … } static int delete_engine_group(struct device *dev, struct otx2_cpt_eng_grp_info *eng_grp) { … } static void update_ucode_ptrs(struct otx2_cpt_eng_grp_info *eng_grp) { … } static int create_engine_group(struct device *dev, struct otx2_cpt_eng_grps *eng_grps, struct otx2_cpt_engines *engs, int ucodes_cnt, void *ucode_data[], int is_print) { … } static void delete_engine_grps(struct pci_dev *pdev, struct otx2_cpt_eng_grps *eng_grps) { … } #define PCI_DEVID_CN10K_RNM … #define RNM_ENTROPY_STATUS … static void rnm_to_cpt_errata_fixup(struct device *dev) { … } int otx2_cpt_get_eng_grp(struct otx2_cpt_eng_grps *eng_grps, int eng_type) { … } int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf, struct otx2_cpt_eng_grps *eng_grps) { … } static int cptx_disable_all_cores(struct otx2_cptpf_dev *cptpf, int total_cores, int blkaddr) { … } int otx2_cpt_disable_all_cores(struct otx2_cptpf_dev *cptpf) { … } void otx2_cpt_cleanup_eng_grps(struct pci_dev *pdev, struct otx2_cpt_eng_grps *eng_grps) { … } int otx2_cpt_init_eng_grps(struct pci_dev *pdev, struct otx2_cpt_eng_grps *eng_grps) { … } static int create_eng_caps_discovery_grps(struct pci_dev *pdev, struct otx2_cpt_eng_grps *eng_grps) { … } /* * Get CPT HW capabilities using LOAD_FVC operation. */ int otx2_cpt_discover_eng_capabilities(struct otx2_cptpf_dev *cptpf) { … } int otx2_cpt_dl_custom_egrp_create(struct otx2_cptpf_dev *cptpf, struct devlink_param_gset_ctx *ctx) { … } int otx2_cpt_dl_custom_egrp_delete(struct otx2_cptpf_dev *cptpf, struct devlink_param_gset_ctx *ctx) { … } static void get_engs_info(struct otx2_cpt_eng_grp_info *eng_grp, char *buf, int size, int idx) { … } void otx2_cpt_print_uc_dbg_info(struct otx2_cptpf_dev *cptpf) { … }
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