// SPDX-License-Identifier: GPL-2.0 /* * Driver for the HiSilicon SEC units found on Hip06 Hip07 * * Copyright (c) 2016-2017 HiSilicon Limited. */ #include <linux/acpi.h> #include <linux/atomic.h> #include <linux/delay.h> #include <linux/dma-direction.h> #include <linux/dma-mapping.h> #include <linux/dmapool.h> #include <linux/io.h> #include <linux/iommu.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqreturn.h> #include <linux/mm.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #include "sec_drv.h" #define SEC_QUEUE_AR_FROCE_ALLOC … #define SEC_QUEUE_AR_FROCE_NOALLOC … #define SEC_QUEUE_AR_FROCE_DIS … #define SEC_QUEUE_AW_FROCE_ALLOC … #define SEC_QUEUE_AW_FROCE_NOALLOC … #define SEC_QUEUE_AW_FROCE_DIS … /* SEC_ALGSUB registers */ #define SEC_ALGSUB_CLK_EN_REG … #define SEC_ALGSUB_CLK_DIS_REG … #define SEC_ALGSUB_CLK_ST_REG … #define SEC_ALGSUB_RST_REQ_REG … #define SEC_ALGSUB_RST_DREQ_REG … #define SEC_ALGSUB_RST_ST_REG … #define SEC_ALGSUB_RST_ST_IS_RST … #define SEC_ALGSUB_BUILD_RST_REQ_REG … #define SEC_ALGSUB_BUILD_RST_DREQ_REG … #define SEC_ALGSUB_BUILD_RST_ST_REG … #define SEC_ALGSUB_BUILD_RST_ST_IS_RST … #define SEC_SAA_BASE … /* SEC_SAA registers */ #define SEC_SAA_CTRL_REG(x) … #define SEC_SAA_CTRL_GET_QM_EN … #define SEC_ST_INTMSK1_REG … #define SEC_ST_RINT1_REG … #define SEC_ST_INTSTS1_REG … #define SEC_BD_MNG_STAT_REG … #define SEC_PARSING_STAT_REG … #define SEC_LOAD_TIME_OUT_CNT_REG … #define SEC_CORE_WORK_TIME_OUT_CNT_REG … #define SEC_BACK_TIME_OUT_CNT_REG … #define SEC_BD1_PARSING_RD_TIME_OUT_CNT_REG … #define SEC_BD1_PARSING_WR_TIME_OUT_CNT_REG … #define SEC_BD2_PARSING_RD_TIME_OUT_CNT_REG … #define SEC_BD2_PARSING_WR_TIME_OUT_CNT_REG … #define SEC_SAA_ACC_REG … #define SEC_BD_NUM_CNT_IN_SEC_REG … #define SEC_LOAD_WORK_TIME_CNT_REG … #define SEC_CORE_WORK_WORK_TIME_CNT_REG … #define SEC_BACK_WORK_TIME_CNT_REG … #define SEC_SAA_IDLE_TIME_CNT_REG … #define SEC_SAA_CLK_CNT_REG … /* SEC_COMMON registers */ #define SEC_CLK_EN_REG … #define SEC_CTRL_REG … #define SEC_COMMON_CNT_CLR_CE_REG … #define SEC_COMMON_CNT_CLR_CE_CLEAR … #define SEC_COMMON_CNT_CLR_CE_SNAP_EN … #define SEC_SECURE_CTRL_REG … #define SEC_AXI_CACHE_CFG_REG … #define SEC_AXI_QOS_CFG_REG … #define SEC_IPV4_MASK_TABLE_REG … #define SEC_IPV6_MASK_TABLE_X_REG(x) … #define SEC_FSM_MAX_CNT_REG … #define SEC_CTRL2_REG … #define SEC_CTRL2_DATA_AXI_RD_OTSD_CFG_M … #define SEC_CTRL2_DATA_AXI_RD_OTSD_CFG_S … #define SEC_CTRL2_DATA_AXI_WR_OTSD_CFG_M … #define SEC_CTRL2_DATA_AXI_WR_OTSD_CFG_S … #define SEC_CTRL2_CLK_GATE_EN … #define SEC_CTRL2_ENDIAN_BD … #define SEC_CTRL2_ENDIAN_BD_TYPE … #define SEC_CNT_PRECISION_CFG_REG … #define SEC_DEBUG_BD_CFG_REG … #define SEC_DEBUG_BD_CFG_WB_NORMAL … #define SEC_DEBUG_BD_CFG_WB_EN … #define SEC_Q_SIGHT_SEL … #define SEC_Q_SIGHT_HIS_CLR … #define SEC_Q_VMID_CFG_REG(q) … #define SEC_Q_WEIGHT_CFG_REG(q) … #define SEC_STAT_CLR_REG … #define SEC_SAA_IDLE_CNT_CLR_REG … #define SEC_QM_CPL_Q_IDBUF_DFX_CFG_REG … #define SEC_QM_CPL_Q_IDBUF_DFX_RESULT_REG … #define SEC_QM_BD_DFX_CFG_REG … #define SEC_QM_BD_DFX_RESULT_REG … #define SEC_QM_BDID_DFX_RESULT_REG … #define SEC_QM_BD_DFIFO_STATUS_REG … #define SEC_QM_BD_DFX_CFG2_REG … #define SEC_QM_BD_DFX_RESULT2_REG … #define SEC_QM_BD_IDFIFO_STATUS_REG … #define SEC_QM_BD_DFIFO_STATUS2_REG … #define SEC_QM_BD_IDFIFO_STATUS2_REG … #define SEC_HASH_IPV4_MASK … #define SEC_MAX_SAA_NUM … #define SEC_SAA_ADDR_SIZE … #define SEC_Q_INIT_REG … #define SEC_Q_INIT_WO_STAT_CLEAR … #define SEC_Q_INIT_AND_STAT_CLEAR … #define SEC_Q_CFG_REG … #define SEC_Q_CFG_REORDER … #define SEC_Q_PROC_NUM_CFG_REG … #define SEC_QUEUE_ENB_REG … #define SEC_Q_DEPTH_CFG_REG … #define SEC_Q_DEPTH_CFG_DEPTH_M … #define SEC_Q_DEPTH_CFG_DEPTH_S … #define SEC_Q_BASE_HADDR_REG … #define SEC_Q_BASE_LADDR_REG … #define SEC_Q_WR_PTR_REG … #define SEC_Q_OUTORDER_BASE_HADDR_REG … #define SEC_Q_OUTORDER_BASE_LADDR_REG … #define SEC_Q_OUTORDER_RD_PTR_REG … #define SEC_Q_OT_TH_REG … #define SEC_Q_ARUSER_CFG_REG … #define SEC_Q_ARUSER_CFG_FA … #define SEC_Q_ARUSER_CFG_FNA … #define SEC_Q_ARUSER_CFG_RINVLD … #define SEC_Q_ARUSER_CFG_PKG … #define SEC_Q_AWUSER_CFG_REG … #define SEC_Q_AWUSER_CFG_FA … #define SEC_Q_AWUSER_CFG_FNA … #define SEC_Q_AWUSER_CFG_PKG … #define SEC_Q_ERR_BASE_HADDR_REG … #define SEC_Q_ERR_BASE_LADDR_REG … #define SEC_Q_CFG_VF_NUM_REG … #define SEC_Q_SOFT_PROC_PTR_REG … #define SEC_Q_FAIL_INT_MSK_REG … #define SEC_Q_FLOW_INT_MKS_REG … #define SEC_Q_FAIL_RINT_REG … #define SEC_Q_FLOW_RINT_REG … #define SEC_Q_FAIL_INT_STATUS_REG … #define SEC_Q_FLOW_INT_STATUS_REG … #define SEC_Q_STATUS_REG … #define SEC_Q_RD_PTR_REG … #define SEC_Q_PRO_PTR_REG … #define SEC_Q_OUTORDER_WR_PTR_REG … #define SEC_Q_OT_CNT_STATUS_REG … #define SEC_Q_INORDER_BD_NUM_ST_REG … #define SEC_Q_INORDER_GET_FLAG_ST_REG … #define SEC_Q_INORDER_ADD_FLAG_ST_REG … #define SEC_Q_INORDER_TASK_INT_NUM_LEFT_ST_REG … #define SEC_Q_RD_DONE_PTR_REG … #define SEC_Q_CPL_Q_BD_NUM_ST_REG … #define SEC_Q_CPL_Q_PTR_ST_REG … #define SEC_Q_CPL_Q_H_ADDR_ST_REG … #define SEC_Q_CPL_Q_L_ADDR_ST_REG … #define SEC_Q_CPL_TASK_INT_NUM_LEFT_ST_REG … #define SEC_Q_WRR_ID_CHECK_REG … #define SEC_Q_CPLQ_FULL_CHECK_REG … #define SEC_Q_SUCCESS_BD_CNT_REG … #define SEC_Q_FAIL_BD_CNT_REG … #define SEC_Q_GET_BD_CNT_REG … #define SEC_Q_IVLD_CNT_REG … #define SEC_Q_BD_PROC_GET_CNT_REG … #define SEC_Q_BD_PROC_DONE_CNT_REG … #define SEC_Q_LAT_CLR_REG … #define SEC_Q_PKT_LAT_MAX_REG … #define SEC_Q_PKT_LAT_AVG_REG … #define SEC_Q_PKT_LAT_MIN_REG … #define SEC_Q_ID_CLR_CFG_REG … #define SEC_Q_1ST_BD_ERR_ID_REG … #define SEC_Q_1ST_AUTH_FAIL_ID_REG … #define SEC_Q_1ST_RD_ERR_ID_REG … #define SEC_Q_1ST_ECC2_ERR_ID_REG … #define SEC_Q_1ST_IVLD_ID_REG … #define SEC_Q_1ST_BD_WR_ERR_ID_REG … #define SEC_Q_1ST_ERR_BD_WR_ERR_ID_REG … #define SEC_Q_1ST_BD_MAC_WR_ERR_ID_REG … struct sec_debug_bd_info { … }; struct sec_out_bd_info { … }; #define SEC_MAX_DEVICES … static struct sec_dev_info *sec_devices[SEC_MAX_DEVICES]; static DEFINE_MUTEX(sec_id_lock); static int sec_queue_map_io(struct sec_queue *queue) { … } static void sec_queue_unmap_io(struct sec_queue *queue) { … } static int sec_queue_ar_pkgattr(struct sec_queue *queue, u32 ar_pkg) { … } static int sec_queue_aw_pkgattr(struct sec_queue *queue, u32 aw_pkg) { … } static int sec_clk_en(struct sec_dev_info *info) { … } static int sec_clk_dis(struct sec_dev_info *info) { … } static int sec_reset_whole_module(struct sec_dev_info *info) { … } static void sec_bd_endian_little(struct sec_dev_info *info) { … } /* * sec_cache_config - configure optimum cache placement */ static void sec_cache_config(struct sec_dev_info *info) { … } static void sec_data_axiwr_otsd_cfg(struct sec_dev_info *info, u32 cfg) { … } static void sec_data_axird_otsd_cfg(struct sec_dev_info *info, u32 cfg) { … } static void sec_clk_gate_en(struct sec_dev_info *info, bool clkgate) { … } static void sec_comm_cnt_cfg(struct sec_dev_info *info, bool clr_ce) { … } static void sec_commsnap_en(struct sec_dev_info *info, bool snap_en) { … } static void sec_ipv6_hashmask(struct sec_dev_info *info, u32 hash_mask[]) { … } static int sec_ipv4_hashmask(struct sec_dev_info *info, u32 hash_mask) { … } static void sec_set_dbg_bd_cfg(struct sec_dev_info *info, u32 cfg) { … } static void sec_saa_getqm_en(struct sec_dev_info *info, u32 saa_indx, u32 en) { … } static void sec_saa_int_mask(struct sec_dev_info *info, u32 saa_indx, u32 saa_int_mask) { … } static void sec_streamid(struct sec_dev_info *info, int i) { … } static void sec_queue_ar_alloc(struct sec_queue *queue, u32 alloc) { … } static void sec_queue_aw_alloc(struct sec_queue *queue, u32 alloc) { … } static void sec_queue_reorder(struct sec_queue *queue, bool reorder) { … } static void sec_queue_depth(struct sec_queue *queue, u32 depth) { … } static void sec_queue_cmdbase_addr(struct sec_queue *queue, u64 addr) { … } static void sec_queue_outorder_addr(struct sec_queue *queue, u64 addr) { … } static void sec_queue_errbase_addr(struct sec_queue *queue, u64 addr) { … } static void sec_queue_irq_disable(struct sec_queue *queue) { … } static void sec_queue_irq_enable(struct sec_queue *queue) { … } static void sec_queue_abn_irq_disable(struct sec_queue *queue) { … } static void sec_queue_stop(struct sec_queue *queue) { … } static void sec_queue_start(struct sec_queue *queue) { … } static struct sec_queue *sec_alloc_queue(struct sec_dev_info *info) { … } static int sec_queue_free(struct sec_queue *queue) { … } static irqreturn_t sec_isr_handle_th(int irq, void *q) { … } static irqreturn_t sec_isr_handle(int irq, void *q) { … } static int sec_queue_irq_init(struct sec_queue *queue) { … } static int sec_queue_irq_uninit(struct sec_queue *queue) { … } static struct sec_dev_info *sec_device_get(void) { … } static struct sec_queue *sec_queue_alloc_start(struct sec_dev_info *info) { … } /** * sec_queue_alloc_start_safe - get a hw queue from appropriate instance * * This function does extremely simplistic load balancing. It does not take into * account NUMA locality of the accelerator, or which cpu has requested the * queue. Future work may focus on optimizing this in order to improve full * machine throughput. */ struct sec_queue *sec_queue_alloc_start_safe(void) { … } /** * sec_queue_stop_release() - free up a hw queue for reuse * @queue: The queue we are done with. * * This will stop the current queue, terminanting any transactions * that are inflight an return it to the pool of available hw queuess */ int sec_queue_stop_release(struct sec_queue *queue) { … } /** * sec_queue_empty() - Is this hardware queue currently empty. * @queue: The queue to test * * We need to know if we have an empty queue for some of the chaining modes * as if it is not empty we may need to hold the message in a software queue * until the hw queue is drained. */ bool sec_queue_empty(struct sec_queue *queue) { … } /** * sec_queue_send() - queue up a single operation in the hw queue * @queue: The queue in which to put the message * @msg: The message * @ctx: Context to be put in the shadow array and passed back to cb on result. * * This function will return -EAGAIN if the queue is currently full. */ int sec_queue_send(struct sec_queue *queue, struct sec_bd_info *msg, void *ctx) { … } bool sec_queue_can_enqueue(struct sec_queue *queue, int num) { … } static void sec_queue_hw_init(struct sec_queue *queue) { … } static int sec_hw_init(struct sec_dev_info *info) { … } static void sec_hw_exit(struct sec_dev_info *info) { … } static void sec_queue_base_init(struct sec_dev_info *info, struct sec_queue *queue, int queue_id) { … } static int sec_map_io(struct sec_dev_info *info, struct platform_device *pdev) { … } static int sec_base_init(struct sec_dev_info *info, struct platform_device *pdev) { … } static void sec_base_exit(struct sec_dev_info *info) { … } #define SEC_Q_CMD_SIZE … #define SEC_Q_CQ_SIZE … #define SEC_Q_DB_SIZE … static int sec_queue_res_cfg(struct sec_queue *queue) { … } static void sec_queue_free_ring_pages(struct sec_queue *queue) { … } static int sec_queue_config(struct sec_dev_info *info, struct sec_queue *queue, int queue_id) { … } static void sec_queue_unconfig(struct sec_dev_info *info, struct sec_queue *queue) { … } static int sec_id_alloc(struct sec_dev_info *info) { … } static void sec_id_free(struct sec_dev_info *info) { … } static int sec_probe(struct platform_device *pdev) { … } static void sec_remove(struct platform_device *pdev) { … } static const __maybe_unused struct of_device_id sec_match[] = …; MODULE_DEVICE_TABLE(of, sec_match); static const __maybe_unused struct acpi_device_id sec_acpi_match[] = …; MODULE_DEVICE_TABLE(acpi, sec_acpi_match); static struct platform_driver sec_driver = …; module_platform_driver(…) …; MODULE_LICENSE(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …;
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