// SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2019 HiSilicon Limited. */ #include <linux/acpi.h> #include <linux/bitops.h> #include <linux/debugfs.h> #include <linux/init.h> #include <linux/io.h> #include <linux/iommu.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/pm_runtime.h> #include <linux/seq_file.h> #include <linux/topology.h> #include <linux/uacce.h> #include "sec.h" #define SEC_VF_NUM … #define SEC_QUEUE_NUM_V1 … #define PCI_DEVICE_ID_HUAWEI_SEC_PF … #define SEC_BD_ERR_CHK_EN0 … #define SEC_BD_ERR_CHK_EN1 … #define SEC_BD_ERR_CHK_EN3 … #define SEC_SQE_SIZE … #define SEC_PF_DEF_Q_NUM … #define SEC_PF_DEF_Q_BASE … #define SEC_CTX_Q_NUM_DEF … #define SEC_CTX_Q_NUM_MAX … #define SEC_CTRL_CNT_CLR_CE … #define SEC_CTRL_CNT_CLR_CE_BIT … #define SEC_CORE_INT_SOURCE … #define SEC_CORE_INT_MASK … #define SEC_CORE_INT_STATUS … #define SEC_CORE_SRAM_ECC_ERR_INFO … #define SEC_ECC_NUM … #define SEC_ECC_MASH … #define SEC_CORE_INT_DISABLE … #define SEC_RAS_CE_REG … #define SEC_RAS_FE_REG … #define SEC_RAS_NFE_REG … #define SEC_RAS_FE_ENB_MSK … #define SEC_OOO_SHUTDOWN_SEL … #define SEC_RAS_DISABLE … #define SEC_MEM_START_INIT_REG … #define SEC_MEM_INIT_DONE_REG … /* clock gating */ #define SEC_CONTROL_REG … #define SEC_DYNAMIC_GATE_REG … #define SEC_CORE_AUTO_GATE … #define SEC_DYNAMIC_GATE_EN … #define SEC_CORE_AUTO_GATE_EN … #define SEC_CLK_GATE_ENABLE … #define SEC_CLK_GATE_DISABLE … #define SEC_TRNG_EN_SHIFT … #define SEC_AXI_SHUTDOWN_ENABLE … #define SEC_AXI_SHUTDOWN_DISABLE … #define SEC_INTERFACE_USER_CTRL0_REG … #define SEC_INTERFACE_USER_CTRL1_REG … #define SEC_SAA_EN_REG … #define SEC_BD_ERR_CHK_EN_REG0 … #define SEC_BD_ERR_CHK_EN_REG1 … #define SEC_BD_ERR_CHK_EN_REG3 … #define SEC_USER0_SMMU_NORMAL … #define SEC_USER1_SMMU_NORMAL … #define SEC_USER1_ENABLE_CONTEXT_SSV … #define SEC_USER1_ENABLE_DATA_SSV … #define SEC_USER1_WB_CONTEXT_SSV … #define SEC_USER1_WB_DATA_SSV … #define SEC_USER1_SVA_SET … #define SEC_USER1_SMMU_SVA … #define SEC_USER1_SMMU_MASK … #define SEC_INTERFACE_USER_CTRL0_REG_V3 … #define SEC_INTERFACE_USER_CTRL1_REG_V3 … #define SEC_USER1_SMMU_NORMAL_V3 … #define SEC_USER1_SMMU_MASK_V3 … #define SEC_CORE_INT_STATUS_M_ECC … #define SEC_PREFETCH_CFG … #define SEC_SVA_TRANS … #define SEC_PREFETCH_ENABLE … #define SEC_PREFETCH_DISABLE … #define SEC_SVA_DISABLE_READY … #define SEC_DELAY_10_US … #define SEC_POLL_TIMEOUT_US … #define SEC_DBGFS_VAL_MAX_LEN … #define SEC_SINGLE_PORT_MAX_TRANS … #define SEC_SQE_MASK_OFFSET … #define SEC_SQE_MASK_LEN … #define SEC_SHAPER_TYPE_RATE … #define SEC_DFX_BASE … #define SEC_DFX_CORE … #define SEC_DFX_COMMON1 … #define SEC_DFX_COMMON2 … #define SEC_DFX_BASE_LEN … #define SEC_DFX_CORE_LEN … #define SEC_DFX_COMMON1_LEN … #define SEC_DFX_COMMON2_LEN … #define SEC_ALG_BITMAP_SHIFT … #define SEC_CIPHER_BITMAP … #define SEC_DIGEST_BITMAP … #define SEC_AEAD_BITMAP … struct sec_hw_error { … }; struct sec_dfx_item { … }; static const char sec_name[] = …; static struct dentry *sec_debugfs_root; static struct hisi_qm_list sec_devices = …; static const struct hisi_qm_cap_info sec_basic_info[] = …; static const u32 sec_pre_store_caps[] = …; static const struct qm_dev_alg sec_dev_algs[] = …; static const struct sec_hw_error sec_hw_errors[] = …; static const char * const sec_dbg_file_name[] = …; static struct sec_dfx_item sec_dfx_labels[] = …; static const struct debugfs_reg32 sec_dfx_regs[] = …; /* define the SEC's dfx regs region and region length */ static struct dfx_diff_registers sec_diff_regs[] = …; static int sec_diff_regs_show(struct seq_file *s, void *unused) { … } DEFINE_SHOW_ATTRIBUTE(…); static bool pf_q_num_flag; static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp) { … } static const struct kernel_param_ops sec_pf_q_num_ops = …; static u32 pf_q_num = …; module_param_cb(…); MODULE_PARM_DESC(…) …; static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp) { … } static const struct kernel_param_ops sec_ctx_q_num_ops = …; static u32 ctx_q_num = …; module_param_cb(…); MODULE_PARM_DESC(…) …; static const struct kernel_param_ops vfs_num_ops = …; static u32 vfs_num; module_param_cb(…); MODULE_PARM_DESC(…) …; void sec_destroy_qps(struct hisi_qp **qps, int qp_num) { … } struct hisi_qp **sec_create_qps(void) { … } u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) { … } static const struct kernel_param_ops sec_uacce_mode_ops = …; /* * uacce_mode = 0 means sec only register to crypto, * uacce_mode = 1 means sec both register to crypto and uacce. */ static u32 uacce_mode = …; module_param_cb(…); MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); static const struct pci_device_id sec_dev_ids[] = …; MODULE_DEVICE_TABLE(pci, sec_dev_ids); static void sec_set_endian(struct hisi_qm *qm) { … } static void sec_engine_sva_config(struct hisi_qm *qm) { … } static void sec_open_sva_prefetch(struct hisi_qm *qm) { … } static void sec_close_sva_prefetch(struct hisi_qm *qm) { … } static void sec_enable_clock_gate(struct hisi_qm *qm) { … } static void sec_disable_clock_gate(struct hisi_qm *qm) { … } static int sec_engine_init(struct hisi_qm *qm) { … } static int sec_set_user_domain_and_cache(struct hisi_qm *qm) { … } /* sec_debug_regs_clear() - clear the sec debug regs */ static void sec_debug_regs_clear(struct hisi_qm *qm) { … } static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable) { … } static void sec_hw_error_enable(struct hisi_qm *qm) { … } static void sec_hw_error_disable(struct hisi_qm *qm) { … } static u32 sec_clear_enable_read(struct hisi_qm *qm) { … } static int sec_clear_enable_write(struct hisi_qm *qm, u32 val) { … } static ssize_t sec_debug_read(struct file *filp, char __user *buf, size_t count, loff_t *pos) { … } static ssize_t sec_debug_write(struct file *filp, const char __user *buf, size_t count, loff_t *pos) { … } static const struct file_operations sec_dbg_fops = …; static int sec_debugfs_atomic64_get(void *data, u64 *val) { … } static int sec_debugfs_atomic64_set(void *data, u64 val) { … } DEFINE_DEBUGFS_ATTRIBUTE(…); static int sec_regs_show(struct seq_file *s, void *unused) { … } DEFINE_SHOW_ATTRIBUTE(…); static int sec_core_debug_init(struct hisi_qm *qm) { … } static int sec_debug_init(struct hisi_qm *qm) { … } static int sec_debugfs_init(struct hisi_qm *qm) { … } static void sec_debugfs_exit(struct hisi_qm *qm) { … } static int sec_show_last_regs_init(struct hisi_qm *qm) { … } static void sec_show_last_regs_uninit(struct hisi_qm *qm) { … } static void sec_show_last_dfx_regs(struct hisi_qm *qm) { … } static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts) { … } static u32 sec_get_hw_err_status(struct hisi_qm *qm) { … } static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) { … } static void sec_open_axi_master_ooo(struct hisi_qm *qm) { … } static void sec_err_info_init(struct hisi_qm *qm) { … } static const struct hisi_qm_err_ini sec_err_ini = …; static int sec_pf_probe_init(struct sec_dev *sec) { … } static int sec_pre_store_cap_reg(struct hisi_qm *qm) { … } static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) { … } static void sec_qm_uninit(struct hisi_qm *qm) { … } static int sec_probe_init(struct sec_dev *sec) { … } static void sec_probe_uninit(struct hisi_qm *qm) { … } static void sec_iommu_used_check(struct sec_dev *sec) { … } static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id) { … } static void sec_remove(struct pci_dev *pdev) { … } static const struct dev_pm_ops sec_pm_ops = …; static const struct pci_error_handlers sec_err_handler = …; static struct pci_driver sec_pci_driver = …; struct pci_driver *hisi_sec_get_pf_driver(void) { … } EXPORT_SYMBOL_GPL(…); static void sec_register_debugfs(void) { … } static void sec_unregister_debugfs(void) { … } static int __init sec_init(void) { … } static void __exit sec_exit(void) { … } module_init(…) …; module_exit(sec_exit); MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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