/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017 MediaTek Inc. * Author: Kevin Chen <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT6797_H #define _DT_BINDINGS_CLK_MT6797_H /* TOPCKGEN */ #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE … #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX … #define CLK_TOP_MUX_AXI … #define CLK_TOP_MUX_MEM … #define CLK_TOP_MUX_DDRPHYCFG … #define CLK_TOP_MUX_MM … #define CLK_TOP_MUX_PWM … #define CLK_TOP_MUX_VDEC … #define CLK_TOP_MUX_VENC … #define CLK_TOP_MUX_MFG … #define CLK_TOP_MUX_CAMTG … #define CLK_TOP_MUX_UART … #define CLK_TOP_MUX_SPI … #define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX … #define CLK_TOP_MUX_USB20 … #define CLK_TOP_MUX_MSDC50_0_HCLK … #define CLK_TOP_MUX_MSDC50_0 … #define CLK_TOP_MUX_MSDC30_1 … #define CLK_TOP_MUX_MSDC30_2 … #define CLK_TOP_MUX_AUDIO … #define CLK_TOP_MUX_AUD_INTBUS … #define CLK_TOP_MUX_PMICSPI … #define CLK_TOP_MUX_SCP … #define CLK_TOP_MUX_ATB … #define CLK_TOP_MUX_MJC … #define CLK_TOP_MUX_DPI0 … #define CLK_TOP_MUX_AUD_1 … #define CLK_TOP_MUX_AUD_2 … #define CLK_TOP_MUX_SSUSB_TOP_SYS … #define CLK_TOP_MUX_SPM … #define CLK_TOP_MUX_BSI_SPI … #define CLK_TOP_MUX_AUDIO_H … #define CLK_TOP_MUX_ANC_MD32 … #define CLK_TOP_MUX_MFG_52M … #define CLK_TOP_SYSPLL_CK … #define CLK_TOP_SYSPLL_D2 … #define CLK_TOP_SYSPLL1_D2 … #define CLK_TOP_SYSPLL1_D4 … #define CLK_TOP_SYSPLL1_D8 … #define CLK_TOP_SYSPLL1_D16 … #define CLK_TOP_SYSPLL_D3 … #define CLK_TOP_SYSPLL_D3_D3 … #define CLK_TOP_SYSPLL2_D2 … #define CLK_TOP_SYSPLL2_D4 … #define CLK_TOP_SYSPLL2_D8 … #define CLK_TOP_SYSPLL_D5 … #define CLK_TOP_SYSPLL3_D2 … #define CLK_TOP_SYSPLL3_D4 … #define CLK_TOP_SYSPLL_D7 … #define CLK_TOP_SYSPLL4_D2 … #define CLK_TOP_SYSPLL4_D4 … #define CLK_TOP_UNIVPLL_CK … #define CLK_TOP_UNIVPLL_D7 … #define CLK_TOP_UNIVPLL_D26 … #define CLK_TOP_SSUSB_PHY_48M_CK … #define CLK_TOP_USB_PHY48M_CK … #define CLK_TOP_UNIVPLL_D2 … #define CLK_TOP_UNIVPLL1_D2 … #define CLK_TOP_UNIVPLL1_D4 … #define CLK_TOP_UNIVPLL1_D8 … #define CLK_TOP_UNIVPLL_D3 … #define CLK_TOP_UNIVPLL2_D2 … #define CLK_TOP_UNIVPLL2_D4 … #define CLK_TOP_UNIVPLL2_D8 … #define CLK_TOP_UNIVPLL_D5 … #define CLK_TOP_UNIVPLL3_D2 … #define CLK_TOP_UNIVPLL3_D4 … #define CLK_TOP_UNIVPLL3_D8 … #define CLK_TOP_ULPOSC_CK_ORG … #define CLK_TOP_ULPOSC_CK … #define CLK_TOP_ULPOSC_D2 … #define CLK_TOP_ULPOSC_D3 … #define CLK_TOP_ULPOSC_D4 … #define CLK_TOP_ULPOSC_D8 … #define CLK_TOP_ULPOSC_D10 … #define CLK_TOP_APLL1_CK … #define CLK_TOP_APLL2_CK … #define CLK_TOP_MFGPLL_CK … #define CLK_TOP_MFGPLL_D2 … #define CLK_TOP_IMGPLL_CK … #define CLK_TOP_IMGPLL_D2 … #define CLK_TOP_IMGPLL_D4 … #define CLK_TOP_CODECPLL_CK … #define CLK_TOP_CODECPLL_D2 … #define CLK_TOP_VDECPLL_CK … #define CLK_TOP_TVDPLL_CK … #define CLK_TOP_TVDPLL_D2 … #define CLK_TOP_TVDPLL_D4 … #define CLK_TOP_TVDPLL_D8 … #define CLK_TOP_TVDPLL_D16 … #define CLK_TOP_MSDCPLL_CK … #define CLK_TOP_MSDCPLL_D2 … #define CLK_TOP_MSDCPLL_D4 … #define CLK_TOP_MSDCPLL_D8 … #define CLK_TOP_NR … /* APMIXED_SYS */ #define CLK_APMIXED_MAINPLL … #define CLK_APMIXED_UNIVPLL … #define CLK_APMIXED_MFGPLL … #define CLK_APMIXED_MSDCPLL … #define CLK_APMIXED_IMGPLL … #define CLK_APMIXED_TVDPLL … #define CLK_APMIXED_CODECPLL … #define CLK_APMIXED_VDECPLL … #define CLK_APMIXED_APLL1 … #define CLK_APMIXED_APLL2 … #define CLK_APMIXED_NR … /* INFRA_SYS */ #define CLK_INFRA_PMIC_TMR … #define CLK_INFRA_PMIC_AP … #define CLK_INFRA_PMIC_MD … #define CLK_INFRA_PMIC_CONN … #define CLK_INFRA_SCP … #define CLK_INFRA_SEJ … #define CLK_INFRA_APXGPT … #define CLK_INFRA_SEJ_13M … #define CLK_INFRA_ICUSB … #define CLK_INFRA_GCE … #define CLK_INFRA_THERM … #define CLK_INFRA_I2C0 … #define CLK_INFRA_I2C1 … #define CLK_INFRA_I2C2 … #define CLK_INFRA_I2C3 … #define CLK_INFRA_PWM_HCLK … #define CLK_INFRA_PWM1 … #define CLK_INFRA_PWM2 … #define CLK_INFRA_PWM3 … #define CLK_INFRA_PWM4 … #define CLK_INFRA_PWM … #define CLK_INFRA_UART0 … #define CLK_INFRA_UART1 … #define CLK_INFRA_UART2 … #define CLK_INFRA_UART3 … #define CLK_INFRA_MD2MD_CCIF_0 … #define CLK_INFRA_MD2MD_CCIF_1 … #define CLK_INFRA_MD2MD_CCIF_2 … #define CLK_INFRA_FHCTL … #define CLK_INFRA_BTIF … #define CLK_INFRA_MD2MD_CCIF_3 … #define CLK_INFRA_SPI … #define CLK_INFRA_MSDC0 … #define CLK_INFRA_MD2MD_CCIF_4 … #define CLK_INFRA_MSDC1 … #define CLK_INFRA_MSDC2 … #define CLK_INFRA_MD2MD_CCIF_5 … #define CLK_INFRA_GCPU … #define CLK_INFRA_TRNG … #define CLK_INFRA_AUXADC … #define CLK_INFRA_CPUM … #define CLK_INFRA_AP_C2K_CCIF_0 … #define CLK_INFRA_AP_C2K_CCIF_1 … #define CLK_INFRA_CLDMA … #define CLK_INFRA_DISP_PWM … #define CLK_INFRA_AP_DMA … #define CLK_INFRA_DEVICE_APC … #define CLK_INFRA_L2C_SRAM … #define CLK_INFRA_CCIF_AP … #define CLK_INFRA_AUDIO … #define CLK_INFRA_CCIF_MD … #define CLK_INFRA_DRAMC_F26M … #define CLK_INFRA_I2C4 … #define CLK_INFRA_I2C_APPM … #define CLK_INFRA_I2C_GPUPM … #define CLK_INFRA_I2C2_IMM … #define CLK_INFRA_I2C2_ARB … #define CLK_INFRA_I2C3_IMM … #define CLK_INFRA_I2C3_ARB … #define CLK_INFRA_I2C5 … #define CLK_INFRA_SYS_CIRQ … #define CLK_INFRA_SPI1 … #define CLK_INFRA_DRAMC_B_F26M … #define CLK_INFRA_ANC_MD32 … #define CLK_INFRA_ANC_MD32_32K … #define CLK_INFRA_DVFS_SPM1 … #define CLK_INFRA_AES_TOP0 … #define CLK_INFRA_AES_TOP1 … #define CLK_INFRA_SSUSB_BUS … #define CLK_INFRA_SPI2 … #define CLK_INFRA_SPI3 … #define CLK_INFRA_SPI4 … #define CLK_INFRA_SPI5 … #define CLK_INFRA_IRTX … #define CLK_INFRA_SSUSB_SYS … #define CLK_INFRA_SSUSB_REF … #define CLK_INFRA_AUDIO_26M … #define CLK_INFRA_AUDIO_26M_PAD_TOP … #define CLK_INFRA_MODEM_TEMP_SHARE … #define CLK_INFRA_VAD_WRAP_SOC … #define CLK_INFRA_DRAMC_CONF … #define CLK_INFRA_DRAMC_B_CONF … #define CLK_INFRA_MFG_VCG … #define CLK_INFRA_13M … #define CLK_INFRA_NR … /* IMG_SYS */ #define CLK_IMG_FDVT … #define CLK_IMG_DPE … #define CLK_IMG_DIP … #define CLK_IMG_LARB6 … #define CLK_IMG_NR … /* MM_SYS */ #define CLK_MM_SMI_COMMON … #define CLK_MM_SMI_LARB0 … #define CLK_MM_SMI_LARB5 … #define CLK_MM_CAM_MDP … #define CLK_MM_MDP_RDMA0 … #define CLK_MM_MDP_RDMA1 … #define CLK_MM_MDP_RSZ0 … #define CLK_MM_MDP_RSZ1 … #define CLK_MM_MDP_RSZ2 … #define CLK_MM_MDP_TDSHP … #define CLK_MM_MDP_COLOR … #define CLK_MM_MDP_WDMA … #define CLK_MM_MDP_WROT0 … #define CLK_MM_MDP_WROT1 … #define CLK_MM_FAKE_ENG … #define CLK_MM_DISP_OVL0 … #define CLK_MM_DISP_OVL1 … #define CLK_MM_DISP_OVL0_2L … #define CLK_MM_DISP_OVL1_2L … #define CLK_MM_DISP_RDMA0 … #define CLK_MM_DISP_RDMA1 … #define CLK_MM_DISP_WDMA0 … #define CLK_MM_DISP_WDMA1 … #define CLK_MM_DISP_COLOR … #define CLK_MM_DISP_CCORR … #define CLK_MM_DISP_AAL … #define CLK_MM_DISP_GAMMA … #define CLK_MM_DISP_OD … #define CLK_MM_DISP_DITHER … #define CLK_MM_DISP_UFOE … #define CLK_MM_DISP_DSC … #define CLK_MM_DISP_SPLIT … #define CLK_MM_DSI0_MM_CLOCK … #define CLK_MM_DSI1_MM_CLOCK … #define CLK_MM_DPI_MM_CLOCK … #define CLK_MM_DPI_INTERFACE_CLOCK … #define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK … #define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK … #define CLK_MM_DISP_OVL0_MOUT_CLOCK … #define CLK_MM_FAKE_ENG2 … #define CLK_MM_DSI0_INTERFACE_CLOCK … #define CLK_MM_DSI1_INTERFACE_CLOCK … #define CLK_MM_NR … /* VDEC_SYS */ #define CLK_VDEC_CKEN_ENG … #define CLK_VDEC_ACTIVE … #define CLK_VDEC_CKEN … #define CLK_VDEC_LARB1_CKEN … #define CLK_VDEC_NR … /* VENC_SYS */ #define CLK_VENC_0 … #define CLK_VENC_1 … #define CLK_VENC_2 … #define CLK_VENC_3 … #define CLK_VENC_NR … #endif /* _DT_BINDINGS_CLK_MT6797_H */
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