/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ /* Copyright(c) 2014 - 2020 Intel Corporation */ #ifndef _ICP_QAT_HW_H_ #define _ICP_QAT_HW_H_ #include <linux/bits.h> enum icp_qat_hw_ae_id { … }; enum icp_qat_hw_qat_id { … }; enum icp_qat_hw_auth_algo { … }; enum icp_qat_hw_auth_mode { … }; struct icp_qat_hw_auth_config { … }; struct icp_qat_hw_ucs_cipher_config { … }; enum icp_qat_slice_mask { … }; enum icp_qat_capabilities_mask { … }; #define QAT_AUTH_MODE_BITPOS … #define QAT_AUTH_MODE_MASK … #define QAT_AUTH_ALGO_BITPOS … #define QAT_AUTH_ALGO_MASK … #define QAT_AUTH_CMP_BITPOS … #define QAT_AUTH_CMP_MASK … #define QAT_AUTH_SHA3_PADDING_BITPOS … #define QAT_AUTH_SHA3_PADDING_MASK … #define QAT_AUTH_ALGO_SHA3_BITPOS … #define QAT_AUTH_ALGO_SHA3_MASK … #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) … struct icp_qat_hw_auth_counter { … }; #define QAT_AUTH_COUNT_MASK … #define QAT_AUTH_COUNT_BITPOS … #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) … struct icp_qat_hw_auth_setup { … }; #define QAT_HW_DEFAULT_ALIGNMENT … #define QAT_HW_ROUND_UP(val, n) … #define ICP_QAT_HW_NULL_STATE1_SZ … #define ICP_QAT_HW_MD5_STATE1_SZ … #define ICP_QAT_HW_SHA1_STATE1_SZ … #define ICP_QAT_HW_SHA224_STATE1_SZ … #define ICP_QAT_HW_SHA256_STATE1_SZ … #define ICP_QAT_HW_SHA3_256_STATE1_SZ … #define ICP_QAT_HW_SHA384_STATE1_SZ … #define ICP_QAT_HW_SHA512_STATE1_SZ … #define ICP_QAT_HW_SHA3_512_STATE1_SZ … #define ICP_QAT_HW_SHA3_224_STATE1_SZ … #define ICP_QAT_HW_SHA3_384_STATE1_SZ … #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ … #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ … #define ICP_QAT_HW_AES_F9_STATE1_SZ … #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ … #define ICP_QAT_HW_GALOIS_128_STATE1_SZ … #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ … #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ … #define ICP_QAT_HW_NULL_STATE2_SZ … #define ICP_QAT_HW_MD5_STATE2_SZ … #define ICP_QAT_HW_SHA1_STATE2_SZ … #define ICP_QAT_HW_SHA224_STATE2_SZ … #define ICP_QAT_HW_SHA256_STATE2_SZ … #define ICP_QAT_HW_SHA3_256_STATE2_SZ … #define ICP_QAT_HW_SHA384_STATE2_SZ … #define ICP_QAT_HW_SHA512_STATE2_SZ … #define ICP_QAT_HW_SHA3_512_STATE2_SZ … #define ICP_QAT_HW_SHA3_224_STATE2_SZ … #define ICP_QAT_HW_SHA3_384_STATE2_SZ … #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ … #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ … #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ … #define ICP_QAT_HW_F9_IK_SZ … #define ICP_QAT_HW_F9_FK_SZ … #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ … #define ICP_QAT_HW_AES_F9_STATE2_SZ … #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ … #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ … #define ICP_QAT_HW_GALOIS_H_SZ … #define ICP_QAT_HW_GALOIS_LEN_A_SZ … #define ICP_QAT_HW_GALOIS_E_CTR0_SZ … struct icp_qat_hw_auth_sha512 { … }; struct icp_qat_hw_auth_algo_blk { … }; #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS … #define ICP_QAT_HW_GALOIS_LEN_A_MASK … enum icp_qat_hw_cipher_algo { … }; enum icp_qat_hw_cipher_mode { … }; struct icp_qat_hw_cipher_config { … }; enum icp_qat_hw_cipher_dir { … }; enum icp_qat_hw_cipher_convert { … }; #define QAT_CIPHER_MODE_BITPOS … #define QAT_CIPHER_MODE_MASK … #define QAT_CIPHER_ALGO_BITPOS … #define QAT_CIPHER_ALGO_MASK … #define QAT_CIPHER_CONVERT_BITPOS … #define QAT_CIPHER_CONVERT_MASK … #define QAT_CIPHER_DIR_BITPOS … #define QAT_CIPHER_DIR_MASK … #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT … #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT … #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) … #define ICP_QAT_HW_DES_BLK_SZ … #define ICP_QAT_HW_3DES_BLK_SZ … #define ICP_QAT_HW_NULL_BLK_SZ … #define ICP_QAT_HW_AES_BLK_SZ … #define ICP_QAT_HW_KASUMI_BLK_SZ … #define ICP_QAT_HW_SNOW_3G_BLK_SZ … #define ICP_QAT_HW_ZUC_3G_BLK_SZ … #define ICP_QAT_HW_NULL_KEY_SZ … #define ICP_QAT_HW_DES_KEY_SZ … #define ICP_QAT_HW_3DES_KEY_SZ … #define ICP_QAT_HW_AES_128_KEY_SZ … #define ICP_QAT_HW_AES_192_KEY_SZ … #define ICP_QAT_HW_AES_256_KEY_SZ … #define ICP_QAT_HW_AES_128_F8_KEY_SZ … #define ICP_QAT_HW_AES_192_F8_KEY_SZ … #define ICP_QAT_HW_AES_256_F8_KEY_SZ … #define ICP_QAT_HW_AES_128_XTS_KEY_SZ … #define ICP_QAT_HW_AES_256_XTS_KEY_SZ … #define ICP_QAT_HW_KASUMI_KEY_SZ … #define ICP_QAT_HW_KASUMI_F8_KEY_SZ … #define ICP_QAT_HW_AES_128_XTS_KEY_SZ … #define ICP_QAT_HW_AES_256_XTS_KEY_SZ … #define ICP_QAT_HW_ARC4_KEY_SZ … #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ … #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ … #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ … #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ … #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR … #define INIT_SHRAM_CONSTANTS_TABLE_SZ … struct icp_qat_hw_cipher_aes256_f8 { … }; struct icp_qat_hw_ucs_cipher_aes256_f8 { … }; struct icp_qat_hw_cipher_algo_blk { … } __aligned(…); enum icp_qat_hw_compression_direction { … }; enum icp_qat_hw_compression_delayed_match { … }; enum icp_qat_hw_compression_algo { … }; enum icp_qat_hw_compression_depth { … }; enum icp_qat_hw_compression_file_type { … }; struct icp_qat_hw_compression_config { … }; #define QAT_COMPRESSION_DIR_BITPOS … #define QAT_COMPRESSION_DIR_MASK … #define QAT_COMPRESSION_DELAYED_MATCH_BITPOS … #define QAT_COMPRESSION_DELAYED_MATCH_MASK … #define QAT_COMPRESSION_ALGO_BITPOS … #define QAT_COMPRESSION_ALGO_MASK … #define QAT_COMPRESSION_DEPTH_BITPOS … #define QAT_COMPRESSION_DEPTH_MASK … #define QAT_COMPRESSION_FILE_TYPE_BITPOS … #define QAT_COMPRESSION_FILE_TYPE_MASK … #define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(dir, delayed, \ algo, depth, filetype) … #endif
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