linux/drivers/clk/mediatek/clk-mt2701.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Shunli Wang <[email protected]>
 */

#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>

#include "clk-cpumux.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"

#include <dt-bindings/clock/mt2701-clk.h>

/*
 * For some clocks, we don't care what their actual rates are. And these
 * clocks may change their rate on different products or different scenarios.
 * So we model these clocks' rate as 0, to denote it's not an actual rate.
 */
#define DUMMY_RATE …

static DEFINE_SPINLOCK(mt2701_clk_lock);

static const struct mtk_fixed_clk top_fixed_clks[] = …;

static const struct mtk_fixed_factor top_fixed_divs[] = …;

static const char * const axi_parents[] = …;

static const char * const mem_parents[] = …;

static const char * const ddrphycfg_parents[] = …;

static const char * const mm_parents[] = …;

static const char * const pwm_parents[] = …;

static const char * const vdec_parents[] = …;

static const char * const mfg_parents[] = …;

static const char * const camtg_parents[] = …;

static const char * const uart_parents[] = …;

static const char * const spi_parents[] = …;

static const char * const usb20_parents[] = …;

static const char * const msdc30_parents[] = …;

static const char * const aud_intbus_parents[] = …;

static const char * const pmicspi_parents[] = …;

static const char * const scp_parents[] = …;

static const char * const dpi0_parents[] = …;

static const char * const dpi1_parents[] = …;

static const char * const tve_parents[] = …;

static const char * const hdmi_parents[] = …;

static const char * const apll_parents[] = …;

static const char * const rtc_parents[] = …;

static const char * const nfi2x_parents[] = …;

static const char * const emmc_hclk_parents[] = …;

static const char * const flash_parents[] = …;

static const char * const di_parents[] = …;

static const char * const nr_osd_parents[] = …;

static const char * const hdmirx_bist_parents[] = …;

static const char * const intdir_parents[] = …;

static const char * const asm_parents[] = …;

static const char * const ms_card_parents[] = …;

static const char * const ethif_parents[] = …;

static const char * const hdmirx_parents[] = …;

static const char * const cmsys_parents[] = …;

static const char * const clk_8bdac_parents[] = …;

static const char * const aud2dvd_parents[] = …;

static const char * const padmclk_parents[] = …;

static const char * const aud_mux_parents[] = …;

static const char * const aud_src_parents[] = …;

static const char * const cpu_parents[] = …;

static const struct mtk_composite cpu_muxes[] __initconst = …;

static const struct mtk_composite top_muxes[] = …;

static const struct mtk_clk_divider top_adj_divs[] = …;

static const struct mtk_gate_regs top_aud_cg_regs = …;

#define GATE_TOP_AUD(_id, _name, _parent, _shift) …

static const struct mtk_gate top_clks[] = …;

static int mtk_topckgen_init(struct platform_device *pdev)
{ … }

static const struct mtk_gate_regs infra_cg_regs = …;

#define GATE_ICG(_id, _name, _parent, _shift) …

static const struct mtk_gate infra_clks[] = …;

static const struct mtk_fixed_factor infra_fixed_divs[] = …;

static u16 infrasys_rst_ofs[] = …;
static u16 pericfg_rst_ofs[] = …;

static const struct mtk_clk_rst_desc clk_rst_desc[] = …;

static struct clk_hw_onecell_data *infra_clk_data;

static void __init mtk_infrasys_init_early(struct device_node *node)
{ … }
CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
			mtk_infrasys_init_early);

static int mtk_infrasys_init(struct platform_device *pdev)
{ … }

static const struct mtk_gate_regs peri0_cg_regs = …;

static const struct mtk_gate_regs peri1_cg_regs = …;

#define GATE_PERI0(_id, _name, _parent, _shift) …

#define GATE_PERI1(_id, _name, _parent, _shift) …

static const struct mtk_gate peri_clks[] = …;

static const char * const uart_ck_sel_parents[] = …;

static const struct mtk_composite peri_muxs[] = …;

static int mtk_pericfg_init(struct platform_device *pdev)
{ … }

#define MT8590_PLL_FMAX …
#define CON0_MT8590_RST_BAR …

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
			_pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) …

static const struct mtk_pll_data apmixed_plls[] = …;

static const struct mtk_fixed_factor apmixed_fixed_divs[] = …;

static int mtk_apmixedsys_init(struct platform_device *pdev)
{ … }

static const struct of_device_id of_match_clk_mt2701[] = …;
MODULE_DEVICE_TABLE(of, of_match_clk_mt2701);

static int clk_mt2701_probe(struct platform_device *pdev)
{ … }

static struct platform_driver clk_mt2701_drv = …;

static int __init clk_mt2701_init(void)
{ … }

arch_initcall(clk_mt2701_init);

MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;