clk-mt6797.c | Explore in Territory

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016 MediaTek Inc.
 * Author: Kevin Chen <[email protected]>
 */

#include <linux/of.h>
#include <linux/platform_device.h>

#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"

#include <dt-bindings/clock/mt6797-clk.h>

/*
 * For some clocks, we don't care what their actual rates are. And these
 * clocks may change their rate on different products or different scenarios.
 * So we model these clocks' rate as 0, to denote it's not an actual rate.
 */

static DEFINE_SPINLOCK(mt6797_clk_lock);

static const struct mtk_fixed_factor top_fixed_divs[] = …;

static const char * const axi_parents[] = …;

static const char * const ulposc_axi_ck_mux_parents[] = …;

static const char * const ulposc_axi_ck_mux_pre_parents[] = …;

static const char * const ddrphycfg_parents[] = …;

static const char * const mm_parents[] = …;

static const char * const pwm_parents[] = …;

static const char * const vdec_parents[] = …;

static const char * const venc_parents[] = …;

static const char * const mfg_parents[] = …;

static const char * const camtg[] = …;

static const char * const uart_parents[] = …;

static const char * const spi_parents[] = …;

static const char * const ulposc_spi_ck_mux_parents[] = …;

static const char * const usb20_parents[] = …;

static const char * const msdc50_0_hclk_parents[] = …;

static const char * const msdc50_0_parents[] = …;

static const char * const msdc30_1_parents[] = …;

static const char * const msdc30_2_parents[] = …;

static const char * const audio_parents[] = …;

static const char * const aud_intbus_parents[] = …;

static const char * const pmicspi_parents[] = …;

static const char * const scp_parents[] = …;

static const char * const atb_parents[] = …;

static const char * const mjc_parents[] = …;

static const char * const dpi0_parents[] = …;

static const char * const aud_1_parents[] = …;

static const char * const aud_2_parents[] = …;

static const char * const ssusb_top_sys_parents[] = …;

static const char * const spm_parents[] = …;

static const char * const bsi_spi_parents[] = …;

static const char * const audio_h_parents[] = …;

static const char * const mfg_52m_parents[] = …;

static const char * const anc_md32_parents[] = …;

/*
 * Clock mux ddrphycfg is needed by the DRAM controller. We mark it as
 * critical as otherwise the system will hang after boot.
 */
static const struct mtk_composite top_muxes[] = …;

static int mtk_topckgen_init(struct platform_device *pdev)
{ … }

static const struct mtk_gate_regs infra0_cg_regs = …;

static const struct mtk_gate_regs infra1_cg_regs = …;

static const struct mtk_gate_regs infra2_cg_regs = …;

#define GATE_ICG0(_id, _name, _parent, _shift) …

#define GATE_ICG1(_id, _name, _parent, _shift) …

#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) …

#define GATE_ICG2(_id, _name, _parent, _shift) …

#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) …

/*
 * Clock gates dramc and dramc_b are needed by the DRAM controller.
 * We mark them as critical as otherwise the system will hang after boot.
 */
static const struct mtk_gate infra_clks[] = …;

static const struct mtk_fixed_factor infra_fixed_divs[] = …;

static struct clk_hw_onecell_data *infra_clk_data;

static void mtk_infrasys_init_early(struct device_node *node)
{ … }

CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg",
		      mtk_infrasys_init_early);

static int mtk_infrasys_init(struct platform_device *pdev)
{ … }

#define MT6797_PLL_FMAX …

#define CON0_MT6797_RST_BAR …

#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
			_pcw_shift, _div_table) …

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
			_pcw_shift) …

static const struct mtk_pll_data plls[] = …;

static int mtk_apmixedsys_init(struct platform_device *pdev)
{ … }

static const struct of_device_id of_match_clk_mt6797[] = …;
MODULE_DEVICE_TABLE(of, of_match_clk_mt6797);

static int clk_mt6797_probe(struct platform_device *pdev)
{ … }

static struct platform_driver clk_mt6797_drv = …;

static int __init clk_mt6797_init(void)
{ … }

arch_initcall(clk_mt6797_init);

MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;
linux/drivers/clk/mediatek/clk-mt6797.c
