linux/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h

/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
/* Copyright(c) 2020 Intel Corporation */
#ifndef ADF_GEN2_HW_DATA_H_
#define ADF_GEN2_HW_DATA_H_

#include "adf_accel_devices.h"
#include "adf_cfg_common.h"

#define ADF_GEN2_RX_RINGS_OFFSET …
#define ADF_GEN2_TX_RINGS_MASK …

/* AE to function map */
#define AE2FUNCTION_MAP_A_OFFSET …
#define AE2FUNCTION_MAP_B_OFFSET …
#define AE2FUNCTION_MAP_REG_SIZE …
#define AE2FUNCTION_MAP_VALID …

#define READ_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index) …
#define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value) …
#define READ_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index) …
#define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value) …

/* Admin Interface Offsets */
#define ADF_ADMINMSGUR_OFFSET …
#define ADF_ADMINMSGLR_OFFSET …
#define ADF_MAILBOX_BASE_OFFSET …

/* Arbiter configuration */
#define ADF_ARB_OFFSET …
#define ADF_ARB_WRK_2_SER_MAP_OFFSET …
#define ADF_ARB_CONFIG …

/* Power gating */
#define ADF_POWERGATE_DC …
#define ADF_POWERGATE_PKE …

/* Default ring mapping */
#define ADF_GEN2_DEFAULT_RING_TO_SRV_MAP …

/* WDT timers
 *
 * Timeout is in cycles. Clock speed may vary across products but this
 * value should be a few milli-seconds.
 */
#define ADF_SSM_WDT_DEFAULT_VALUE …
#define ADF_SSM_WDT_PKE_DEFAULT_VALUE …
#define ADF_SSMWDT_OFFSET …
#define ADF_SSMWDTPKE_OFFSET …
#define ADF_SSMWDT(i) …
#define ADF_SSMWDTPKE(i) …

/* Error detection and correction */
#define ADF_GEN2_AE_CTX_ENABLES(i) …
#define ADF_GEN2_AE_MISC_CONTROL(i) …
#define ADF_GEN2_ENABLE_AE_ECC_ERR …
#define ADF_GEN2_ENABLE_AE_ECC_PARITY_CORR …
#define ADF_GEN2_UERRSSMSH(i) …
#define ADF_GEN2_CERRSSMSH(i) …
#define ADF_GEN2_ERRSSMSH_EN …

/* Number of heartbeat counter pairs */
#define ADF_NUM_HB_CNT_PER_AE …

/* Interrupts */
#define ADF_GEN2_SMIAPF0_MASK_OFFSET …
#define ADF_GEN2_SMIAPF1_MASK_OFFSET …
#define ADF_GEN2_SMIA1_MASK …

u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self);
u32 adf_gen2_get_num_aes(struct adf_hw_device_data *self);
void adf_gen2_enable_error_correction(struct adf_accel_dev *accel_dev);
void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
			   int num_a_regs, int num_b_regs);
void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info);
void adf_gen2_get_arb_info(struct arb_info *arb_info);
void adf_gen2_enable_ints(struct adf_accel_dev *accel_dev);
u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev);
void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);

#endif