/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ /* Copyright(c) 2020 Intel Corporation */ #ifndef ADF_GEN4_HW_DATA_H_ #define ADF_GEN4_HW_DATA_H_ #include <linux/units.h> #include "adf_accel_devices.h" #include "adf_cfg_common.h" /* PCIe configuration space */ #define ADF_GEN4_BAR_MASK … #define ADF_GEN4_SRAM_BAR … #define ADF_GEN4_PMISC_BAR … #define ADF_GEN4_ETR_BAR … /* Clocks frequency */ #define ADF_GEN4_KPT_COUNTER_FREQ … /* Physical function fuses */ #define ADF_GEN4_FUSECTL0_OFFSET … #define ADF_GEN4_FUSECTL1_OFFSET … #define ADF_GEN4_FUSECTL2_OFFSET … #define ADF_GEN4_FUSECTL3_OFFSET … #define ADF_GEN4_FUSECTL4_OFFSET … #define ADF_GEN4_FUSECTL5_OFFSET … /* Accelerators */ #define ADF_GEN4_ACCELERATORS_MASK … #define ADF_GEN4_MAX_ACCELERATORS … #define ADF_GEN4_ADMIN_ACCELENGINES … /* MSIX interrupt */ #define ADF_GEN4_SMIAPF_RP_X0_MASK_OFFSET … #define ADF_GEN4_SMIAPF_RP_X1_MASK_OFFSET … #define ADF_GEN4_SMIAPF_MASK_OFFSET … #define ADF_GEN4_MSIX_RTTABLE_OFFSET(i) … /* Bank and ring configuration */ #define ADF_GEN4_MAX_RPS … #define ADF_GEN4_NUM_RINGS_PER_BANK … #define ADF_GEN4_NUM_BANKS_PER_VF … #define ADF_GEN4_ETR_MAX_BANKS … #define ADF_GEN4_RX_RINGS_OFFSET … #define ADF_GEN4_TX_RINGS_MASK … /* Arbiter configuration */ #define ADF_GEN4_ARB_CONFIG … #define ADF_GEN4_ARB_OFFSET … #define ADF_GEN4_ARB_WRK_2_SER_MAP_OFFSET … /* Admin Interface Reg Offset */ #define ADF_GEN4_ADMINMSGUR_OFFSET … #define ADF_GEN4_ADMINMSGLR_OFFSET … #define ADF_GEN4_MAILBOX_BASE_OFFSET … /* Default ring mapping */ #define ADF_GEN4_DEFAULT_RING_TO_SRV_MAP … /* WDT timers * * Timeout is in cycles. Clock speed may vary across products but this * value should be a few milli-seconds. */ #define ADF_SSM_WDT_DEFAULT_VALUE … #define ADF_SSM_WDT_PKE_DEFAULT_VALUE … #define ADF_SSMWDTL_OFFSET … #define ADF_SSMWDTH_OFFSET … #define ADF_SSMWDTPKEL_OFFSET … #define ADF_SSMWDTPKEH_OFFSET … /* Ring reset */ #define ADF_RPRESET_POLL_TIMEOUT_US … #define ADF_RPRESET_POLL_DELAY_US … #define ADF_WQM_CSR_RPRESETCTL_RESET … #define ADF_WQM_CSR_RPRESETCTL_DRAIN … #define ADF_WQM_CSR_RPRESETCTL(bank) … #define ADF_WQM_CSR_RPRESETSTS_STATUS … #define ADF_WQM_CSR_RPRESETSTS(bank) … /* Ring interrupt */ #define ADF_RP_INT_SRC_SEL_F_RISE_MASK … #define ADF_RP_INT_SRC_SEL_F_FALL_MASK … #define ADF_RP_INT_SRC_SEL_RANGE_WIDTH … #define ADF_COALESCED_POLL_TIMEOUT_US … #define ADF_COALESCED_POLL_DELAY_US … #define ADF_WQM_CSR_RPINTSOU(bank) … #define ADF_WQM_CSR_RP_IDX_RX … /* Error source registers */ #define ADF_GEN4_ERRSOU0 … #define ADF_GEN4_ERRSOU1 … #define ADF_GEN4_ERRSOU2 … #define ADF_GEN4_ERRSOU3 … /* Error source mask registers */ #define ADF_GEN4_ERRMSK0 … #define ADF_GEN4_ERRMSK1 … #define ADF_GEN4_ERRMSK2 … #define ADF_GEN4_ERRMSK3 … #define ADF_GEN4_VFLNOTIFY … /* Number of heartbeat counter pairs */ #define ADF_NUM_HB_CNT_PER_AE … /* Rate Limiting */ #define ADF_GEN4_RL_R2L_OFFSET … #define ADF_GEN4_RL_L2C_OFFSET … #define ADF_GEN4_RL_C2S_OFFSET … #define ADF_GEN4_RL_TOKEN_PCIEIN_BUCKET_OFFSET … #define ADF_GEN4_RL_TOKEN_PCIEOUT_BUCKET_OFFSET … /* Arbiter threads mask with error value */ #define ADF_GEN4_ENA_THD_MASK_ERROR … /* PF2VM communication channel */ #define ADF_GEN4_PF2VM_OFFSET(i) … #define ADF_GEN4_VM2PF_OFFSET(i) … #define ADF_GEN4_VINTMSKPF2VM_OFFSET(i) … #define ADF_GEN4_VINTSOUPF2VM_OFFSET(i) … #define ADF_GEN4_VINTMSK_OFFSET(i) … #define ADF_GEN4_VINTSOU_OFFSET(i) … struct adf_gen4_vfmig { … }; void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev); enum icp_qat_gen4_slice_mask { … }; enum adf_gen4_rp_groups { … }; void adf_gen4_enable_error_correction(struct adf_accel_dev *accel_dev); void adf_gen4_enable_ints(struct adf_accel_dev *accel_dev); u32 adf_gen4_get_accel_mask(struct adf_hw_device_data *self); void adf_gen4_get_admin_info(struct admin_info *admin_csrs_info); void adf_gen4_get_arb_info(struct arb_info *arb_info); u32 adf_gen4_get_etr_bar_id(struct adf_hw_device_data *self); u32 adf_gen4_get_heartbeat_clock(struct adf_hw_device_data *self); u32 adf_gen4_get_misc_bar_id(struct adf_hw_device_data *self); u32 adf_gen4_get_num_accels(struct adf_hw_device_data *self); u32 adf_gen4_get_num_aes(struct adf_hw_device_data *self); enum dev_sku_info adf_gen4_get_sku(struct adf_hw_device_data *self); u32 adf_gen4_get_sram_bar_id(struct adf_hw_device_data *self); int adf_gen4_init_device(struct adf_accel_dev *accel_dev); int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number); void adf_gen4_set_msix_default_rttable(struct adf_accel_dev *accel_dev); void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev); int adf_gen4_init_thd2arb_map(struct adf_accel_dev *accel_dev); u16 adf_gen4_get_ring_to_svc_map(struct adf_accel_dev *accel_dev); int adf_gen4_bank_quiesce_coal_timer(struct adf_accel_dev *accel_dev, u32 bank_idx, int timeout_ms); int adf_gen4_bank_drain_start(struct adf_accel_dev *accel_dev, u32 bank_number, int timeout_us); void adf_gen4_bank_drain_finish(struct adf_accel_dev *accel_dev, u32 bank_number); int adf_gen4_bank_state_save(struct adf_accel_dev *accel_dev, u32 bank_number, struct bank_state *state); int adf_gen4_bank_state_restore(struct adf_accel_dev *accel_dev, u32 bank_number, struct bank_state *state); #endif
Codebase Browser
linux