icp_qat_fw_comp.h | Explore in Territory

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright(c) 2022 Intel Corporation */
#ifndef _ICP_QAT_FW_COMP_H_
#define _ICP_QAT_FW_COMP_H_
#include "icp_qat_fw.h"

enum icp_qat_fw_comp_cmd_id { … };

enum icp_qat_fw_comp_20_cmd_id { … };

#define ICP_QAT_FW_COMP_STATELESS_SESSION …
#define ICP_QAT_FW_COMP_STATEFUL_SESSION …
#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST …
#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST …
#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST …
#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST …
#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST …
#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST …
#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF …
#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF …
#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS …
#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK …
#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS …
#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK …
#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS …
#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK …
#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS …
#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK …
#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS …
#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK …

#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
	ret_uncomp, secure_ram) …

#define ICP_QAT_FW_COMP_SESSION_TYPE_GET(flags) …

#define ICP_QAT_FW_COMP_SESSION_TYPE_SET(flags, val) …

#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_GET(flags) …

#define ICP_QAT_FW_COMP_EN_ASB_GET(flags) …

#define ICP_QAT_FW_COMP_RET_UNCOMP_GET(flags) …

#define ICP_QAT_FW_COMP_SECURE_RAM_USE_GET(flags) …

struct icp_qat_fw_comp_req_hdr_cd_pars { … };

struct icp_qat_fw_comp_req_params { … };

#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr, \
					      cnvdfx, crc, xxhash_acc, \
					      cnv_error_type, append_crc, \
					      drop_data) …

#define ICP_QAT_FW_COMP_NOT_SOP …
#define ICP_QAT_FW_COMP_SOP …
#define ICP_QAT_FW_COMP_NOT_EOP …
#define ICP_QAT_FW_COMP_EOP …
#define ICP_QAT_FW_COMP_NOT_BFINAL …
#define ICP_QAT_FW_COMP_BFINAL …
#define ICP_QAT_FW_COMP_NO_CNV …
#define ICP_QAT_FW_COMP_CNV …
#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY …
#define ICP_QAT_FW_COMP_CNV_RECOVERY …
#define ICP_QAT_FW_COMP_NO_CNV_DFX …
#define ICP_QAT_FW_COMP_CNV_DFX …
#define ICP_QAT_FW_COMP_CRC_MODE_LEGACY …
#define ICP_QAT_FW_COMP_CRC_MODE_E2E …
#define ICP_QAT_FW_COMP_NO_XXHASH_ACC …
#define ICP_QAT_FW_COMP_XXHASH_ACC …
#define ICP_QAT_FW_COMP_APPEND_CRC …
#define ICP_QAT_FW_COMP_NO_APPEND_CRC …
#define ICP_QAT_FW_COMP_DROP_DATA …
#define ICP_QAT_FW_COMP_NO_DROP_DATA …
#define ICP_QAT_FW_COMP_SOP_BITPOS …
#define ICP_QAT_FW_COMP_SOP_MASK …
#define ICP_QAT_FW_COMP_EOP_BITPOS …
#define ICP_QAT_FW_COMP_EOP_MASK …
#define ICP_QAT_FW_COMP_BFINAL_BITPOS …
#define ICP_QAT_FW_COMP_BFINAL_MASK …
#define ICP_QAT_FW_COMP_CNV_BITPOS …
#define ICP_QAT_FW_COMP_CNV_MASK …
#define ICP_QAT_FW_COMP_CNVNR_BITPOS …
#define ICP_QAT_FW_COMP_CNVNR_MASK …
#define ICP_QAT_FW_COMP_CNV_DFX_BITPOS …
#define ICP_QAT_FW_COMP_CNV_DFX_MASK …
#define ICP_QAT_FW_COMP_CRC_MODE_BITPOS …
#define ICP_QAT_FW_COMP_CRC_MODE_MASK …
#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS …
#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK …
#define ICP_QAT_FW_COMP_CNV_ERROR_BITPOS …
#define ICP_QAT_FW_COMP_CNV_ERROR_MASK …
#define ICP_QAT_FW_COMP_CNV_ERROR_NONE …
#define ICP_QAT_FW_COMP_CNV_ERROR_CHECKSUM …
#define ICP_QAT_FW_COMP_CNV_ERROR_DCPR_OBC_DIFF …
#define ICP_QAT_FW_COMP_CNV_ERROR_DCPR …
#define ICP_QAT_FW_COMP_CNV_ERROR_XLT …
#define ICP_QAT_FW_COMP_CNV_ERROR_DCPR_IBC_DIFF …
#define ICP_QAT_FW_COMP_APPEND_CRC_BITPOS …
#define ICP_QAT_FW_COMP_APPEND_CRC_MASK …
#define ICP_QAT_FW_COMP_DROP_DATA_BITPOS …
#define ICP_QAT_FW_COMP_DROP_DATA_MASK …

#define ICP_QAT_FW_COMP_SOP_GET(flags) …

#define ICP_QAT_FW_COMP_SOP_SET(flags, val) …

#define ICP_QAT_FW_COMP_EOP_GET(flags) …

#define ICP_QAT_FW_COMP_EOP_SET(flags, val) …

#define ICP_QAT_FW_COMP_BFINAL_GET(flags) …

#define ICP_QAT_FW_COMP_BFINAL_SET(flags, val) …

#define ICP_QAT_FW_COMP_CNV_GET(flags) …

#define ICP_QAT_FW_COMP_CNVNR_GET(flags) …

#define ICP_QAT_FW_COMP_CNV_DFX_GET(flags) …

#define ICP_QAT_FW_COMP_CNV_DFX_SET(flags, val) …

#define ICP_QAT_FW_COMP_CRC_MODE_GET(flags) …

#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_GET(flags) …

#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_SET(flags, val) …

#define ICP_QAT_FW_COMP_CNV_ERROR_TYPE_GET(flags) …

#define ICP_QAT_FW_COMP_CNV_ERROR_TYPE_SET(flags, val) …

struct icp_qat_fw_xlt_req_params { … };

struct icp_qat_fw_comp_cd_hdr { … };

#define COMP_CPR_INITIAL_CRC …
#define COMP_CPR_INITIAL_ADLER …

struct icp_qat_fw_xlt_cd_hdr { … };

struct icp_qat_fw_comp_req { … };

struct icp_qat_fw_resp_comp_pars { … };

struct icp_qat_fw_comp_state { … };

struct icp_qat_fw_comp_resp { … };

#define QAT_FW_COMP_BANK_FLAG_MASK …
#define QAT_FW_COMP_BANK_I_BITPOS …
#define QAT_FW_COMP_BANK_H_BITPOS …
#define QAT_FW_COMP_BANK_G_BITPOS …
#define QAT_FW_COMP_BANK_F_BITPOS …
#define QAT_FW_COMP_BANK_E_BITPOS …
#define QAT_FW_COMP_BANK_D_BITPOS …
#define QAT_FW_COMP_BANK_C_BITPOS …
#define QAT_FW_COMP_BANK_B_BITPOS …
#define QAT_FW_COMP_BANK_A_BITPOS …

enum icp_qat_fw_comp_bank_enabled { … };

#define ICP_QAT_FW_COMP_RAM_FLAGS_BUILD(bank_i_enable, bank_h_enable, \
					bank_g_enable, bank_f_enable, \
					bank_e_enable, bank_d_enable, \
					bank_c_enable, bank_b_enable, \
					bank_a_enable) …

struct icp_qat_fw_comp_crc_data_struct { … };

struct xxhash_acc_state_buff { … };

#endif
linux/drivers/crypto/intel/qat/qat_common/icp_qat_fw_comp.h
