/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright(c) 2022 Intel Corporation */ #ifndef _ICP_QAT_HW_20_COMP_DEFS_H #define _ICP_QAT_HW_20_COMP_DEFS_H #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK … enum icp_qat_hw_comp_20_scb_control { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK … enum icp_qat_hw_comp_20_rmb_control { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK … enum icp_qat_hw_comp_20_som_control { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK … enum icp_qat_hw_comp_20_skip_hash_rd_control { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK … enum icp_qat_hw_comp_20_scb_unload_control { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK … enum icp_qat_hw_comp_20_disable_token_fusion_control { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK … enum icp_qat_hw_comp_20_lbms { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK … enum icp_qat_hw_comp_20_scb_mode_reset_mask { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK … enum icp_qat_hw_comp_20_hbs_control { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK … enum icp_qat_hw_comp_20_abd { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK … enum icp_qat_hw_comp_20_lllbd_ctrl { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK … enum icp_qat_hw_comp_20_search_depth { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK … enum icp_qat_hw_comp_20_hw_comp_format { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK … enum icp_qat_hw_comp_20_min_match_control { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK … enum icp_qat_hw_comp_20_skip_hash_collision { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK … enum icp_qat_hw_comp_20_skip_hash_update { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK … enum icp_qat_hw_comp_20_byte_skip { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_DEFAULT_VAL … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS … #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK … enum icp_qat_hw_comp_20_extended_delay_match_mode { … }; #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_DEFAULT_VAL … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK … enum icp_qat_hw_decomp_20_speculative_decoder_control { … }; #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_BITPOS … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_MASK … enum icp_qat_hw_decomp_20_mini_cam_control { … }; #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK … enum icp_qat_hw_decomp_20_hbs_control { … }; #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_BITPOS … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK … enum icp_qat_hw_decomp_20_lbms { … }; #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_DEFAULT_VAL … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK … enum icp_qat_hw_decomp_20_hw_comp_format { … }; #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_DEFAULT_VAL … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK … enum icp_qat_hw_decomp_20_min_match_control { … }; #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_BITPOS … #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_MASK … enum icp_qat_hw_decomp_20_lz4_block_checksum_present { … }; #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_DEFAULT_VAL … #endif
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