linux/drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
/* Copyright(c) 2014 - 2021 Intel Corporation */
#include <adf_accel_devices.h>
#include <adf_admin.h>
#include <adf_common_drv.h>
#include <adf_gen2_config.h>
#include <adf_gen2_dc.h>
#include <adf_gen2_hw_csr_data.h>
#include <adf_gen2_hw_data.h>
#include <adf_gen2_pfvf.h>
#include "adf_dh895xcc_hw_data.h"
#include "adf_heartbeat.h"
#include "icp_qat_hw.h"

#define ADF_DH895XCC_VF_MSK …

/* Worker thread to service arbiter mappings */
static const u32 thrd_to_arb_map[ADF_DH895XCC_MAX_ACCELENGINES] = …;

static struct adf_hw_device_class dh895xcc_class = …;

static u32 get_accel_mask(struct adf_hw_device_data *self)
{ … }

static u32 get_ae_mask(struct adf_hw_device_data *self)
{ … }

static u32 get_misc_bar_id(struct adf_hw_device_data *self)
{ … }

static u32 get_ts_clock(struct adf_hw_device_data *self)
{ … }

static u32 get_etr_bar_id(struct adf_hw_device_data *self)
{ … }

static u32 get_sram_bar_id(struct adf_hw_device_data *self)
{ … }

static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
{ … }

static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
{ … }

static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)
{ … }

static void enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
{ … }

static void disable_all_vf2pf_interrupts(void __iomem *pmisc_addr)
{ … }

static u32 disable_pending_vf2pf_interrupts(void __iomem *pmisc_addr)
{ … }

static void configure_iov_threads(struct adf_accel_dev *accel_dev, bool enable)
{ … }

void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
{ … }

void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
{ … }