/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright(c) 2023 Intel Corporation */ #ifndef ADF_420XX_HW_DATA_H_ #define ADF_420XX_HW_DATA_H_ #include <adf_accel_devices.h> #define ADF_420XX_MAX_ACCELENGINES … #define ADF_420XX_ACCELENGINES_MASK … #define ADF_420XX_ADMIN_AE_MASK … #define ADF_420XX_HICPPAGENTCMDPARERRLOG_MASK … #define ADF_420XX_PARITYERRORMASK_ATH_CPH_MASK … #define ADF_420XX_PARITYERRORMASK_CPR_XLT_MASK … #define ADF_420XX_PARITYERRORMASK_DCPR_UCS_MASK … #define ADF_420XX_PARITYERRORMASK_PKE_MASK … #define ADF_420XX_PARITYERRORMASK_WAT_WCP_MASK … /* * SSMFEATREN bit mask * BIT(4) - enables parity detection on CPP * BIT(12) - enables the logging of push/pull data errors * in pperr register * BIT(16) - BIT(27) - enable parity detection on SPPs */ #define ADF_420XX_SSMFEATREN_MASK … /* Firmware Binaries */ #define ADF_420XX_FW … #define ADF_420XX_MMP … #define ADF_420XX_SYM_OBJ … #define ADF_420XX_DC_OBJ … #define ADF_420XX_ASYM_OBJ … #define ADF_420XX_ADMIN_OBJ … /* RL constants */ #define ADF_420XX_RL_PCIE_SCALE_FACTOR_DIV … #define ADF_420XX_RL_PCIE_SCALE_FACTOR_MUL … #define ADF_420XX_RL_DCPR_CORRECTION … #define ADF_420XX_RL_SCANS_PER_SEC … #define ADF_420XX_RL_MAX_TP_ASYM … #define ADF_420XX_RL_MAX_TP_SYM … #define ADF_420XX_RL_MAX_TP_DC … #define ADF_420XX_RL_SLICE_REF … /* Clocks frequency */ #define ADF_420XX_AE_FREQ … void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id); void adf_clean_hw_data_420xx(struct adf_hw_device_data *hw_data); #endif
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