/* SPDX-License-Identifier: GPL-2.0-only */ /* include/linux/amba/pl080.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <[email protected]> * * ARM PrimeCell PL080 DMA controller */ /* Note, there are some Samsung updates to this controller block which * make it not entierly compatible with the PL080 specification from * ARM. When in doubt, check the Samsung documentation first. * * The Samsung defines are PL080S, and add an extra control register, * the ability to move more than 2^11 counts of data and some extra * OneNAND features. */ #ifndef ASM_PL080_H #define ASM_PL080_H #define PL080_INT_STATUS … #define PL080_TC_STATUS … #define PL080_TC_CLEAR … #define PL080_ERR_STATUS … #define PL080_ERR_CLEAR … #define PL080_RAW_TC_STATUS … #define PL080_RAW_ERR_STATUS … #define PL080_EN_CHAN … #define PL080_SOFT_BREQ … #define PL080_SOFT_SREQ … #define PL080_SOFT_LBREQ … #define PL080_SOFT_LSREQ … #define PL080_CONFIG … #define PL080_CONFIG_M2_BE … #define PL080_CONFIG_M1_BE … #define PL080_CONFIG_ENABLE … #define PL080_SYNC … /* The Faraday Technology FTDMAC020 variant registers */ #define FTDMAC020_CH_BUSY … /* Identical to PL080_CONFIG */ #define FTDMAC020_CSR … /* Identical to PL080_SYNC */ #define FTDMAC020_SYNC … #define FTDMAC020_REVISION … #define FTDMAC020_FEATURE … /* Per channel configuration registers */ #define PL080_Cx_BASE(x) … #define PL080_CH_SRC_ADDR … #define PL080_CH_DST_ADDR … #define PL080_CH_LLI … #define PL080_CH_CONTROL … #define PL080_CH_CONFIG … #define PL080S_CH_CONTROL2 … #define PL080S_CH_CONFIG … /* The Faraday FTDMAC020 derivative shuffles the registers around */ #define FTDMAC020_CH_CSR … #define FTDMAC020_CH_CFG … #define FTDMAC020_CH_SRC_ADDR … #define FTDMAC020_CH_DST_ADDR … #define FTDMAC020_CH_LLP … #define FTDMAC020_CH_SIZE … #define PL080_LLI_ADDR_MASK … #define PL080_LLI_ADDR_SHIFT … #define PL080_LLI_LM_AHB2 … #define PL080_CONTROL_TC_IRQ_EN … #define PL080_CONTROL_PROT_MASK … #define PL080_CONTROL_PROT_SHIFT … #define PL080_CONTROL_PROT_CACHE … #define PL080_CONTROL_PROT_BUFF … #define PL080_CONTROL_PROT_SYS … #define PL080_CONTROL_DST_INCR … #define PL080_CONTROL_SRC_INCR … #define PL080_CONTROL_DST_AHB2 … #define PL080_CONTROL_SRC_AHB2 … #define PL080_CONTROL_DWIDTH_MASK … #define PL080_CONTROL_DWIDTH_SHIFT … #define PL080_CONTROL_SWIDTH_MASK … #define PL080_CONTROL_SWIDTH_SHIFT … #define PL080_CONTROL_DB_SIZE_MASK … #define PL080_CONTROL_DB_SIZE_SHIFT … #define PL080_CONTROL_SB_SIZE_MASK … #define PL080_CONTROL_SB_SIZE_SHIFT … #define PL080_CONTROL_TRANSFER_SIZE_MASK … #define PL080S_CONTROL_TRANSFER_SIZE_MASK … #define PL080_CONTROL_TRANSFER_SIZE_SHIFT … #define PL080_BSIZE_1 … #define PL080_BSIZE_4 … #define PL080_BSIZE_8 … #define PL080_BSIZE_16 … #define PL080_BSIZE_32 … #define PL080_BSIZE_64 … #define PL080_BSIZE_128 … #define PL080_BSIZE_256 … #define PL080_WIDTH_8BIT … #define PL080_WIDTH_16BIT … #define PL080_WIDTH_32BIT … #define PL080N_CONFIG_ITPROT … #define PL080N_CONFIG_SECPROT … #define PL080_CONFIG_HALT … #define PL080_CONFIG_ACTIVE … #define PL080_CONFIG_LOCK … #define PL080_CONFIG_TC_IRQ_MASK … #define PL080_CONFIG_ERR_IRQ_MASK … #define PL080_CONFIG_FLOW_CONTROL_MASK … #define PL080_CONFIG_FLOW_CONTROL_SHIFT … #define PL080_CONFIG_DST_SEL_MASK … #define PL080_CONFIG_DST_SEL_SHIFT … #define PL080_CONFIG_SRC_SEL_MASK … #define PL080_CONFIG_SRC_SEL_SHIFT … #define PL080_CONFIG_ENABLE … #define PL080_FLOW_MEM2MEM … #define PL080_FLOW_MEM2PER … #define PL080_FLOW_PER2MEM … #define PL080_FLOW_SRC2DST … #define PL080_FLOW_SRC2DST_DST … #define PL080_FLOW_MEM2PER_PER … #define PL080_FLOW_PER2MEM_PER … #define PL080_FLOW_SRC2DST_SRC … #define FTDMAC020_CH_CSR_TC_MSK … /* Later versions have a threshold in bits 24..26, */ #define FTDMAC020_CH_CSR_FIFOTH_MSK … #define FTDMAC020_CH_CSR_FIFOTH_SHIFT … #define FTDMAC020_CH_CSR_CHPR1_MSK … #define FTDMAC020_CH_CSR_PROT3 … #define FTDMAC020_CH_CSR_PROT2 … #define FTDMAC020_CH_CSR_PROT1 … #define FTDMAC020_CH_CSR_SRC_SIZE_MSK … #define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT … #define FTDMAC020_CH_CSR_ABT … #define FTDMAC020_CH_CSR_SRC_WIDTH_MSK … #define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT … #define FTDMAC020_CH_CSR_DST_WIDTH_MSK … #define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT … #define FTDMAC020_CH_CSR_MODE … /* 00 = increase, 01 = decrease, 10 = fix */ #define FTDMAC020_CH_CSR_SRCAD_CTL_MSK … #define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT … #define FTDMAC020_CH_CSR_DSTAD_CTL_MSK … #define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT … #define FTDMAC020_CH_CSR_SRC_SEL … #define FTDMAC020_CH_CSR_DST_SEL … #define FTDMAC020_CH_CSR_EN … /* FIFO threshold setting */ #define FTDMAC020_CH_CSR_FIFOTH_1 … #define FTDMAC020_CH_CSR_FIFOTH_2 … #define FTDMAC020_CH_CSR_FIFOTH_4 … #define FTDMAC020_CH_CSR_FIFOTH_8 … #define FTDMAC020_CH_CSR_FIFOTH_16 … /* The FTDMAC020 supports 64bit wide transfers */ #define FTDMAC020_WIDTH_64BIT … /* Address can be increased, decreased or fixed */ #define FTDMAC020_CH_CSR_SRCAD_CTL_INC … #define FTDMAC020_CH_CSR_SRCAD_CTL_DEC … #define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED … #define FTDMAC020_CH_CFG_LLP_CNT_MASK … #define FTDMAC020_CH_CFG_LLP_CNT_SHIFT … #define FTDMAC020_CH_CFG_BUSY … #define FTDMAC020_CH_CFG_INT_ABT_MASK … #define FTDMAC020_CH_CFG_INT_ERR_MASK … #define FTDMAC020_CH_CFG_INT_TC_MASK … /* Inside the LLIs, the applicable CSR fields are mapped differently */ #define FTDMAC020_LLI_TC_MSK … #define FTDMAC020_LLI_SRC_WIDTH_MSK … #define FTDMAC020_LLI_SRC_WIDTH_SHIFT … #define FTDMAC020_LLI_DST_WIDTH_MSK … #define FTDMAC020_LLI_DST_WIDTH_SHIFT … #define FTDMAC020_LLI_SRCAD_CTL_MSK … #define FTDMAC020_LLI_SRCAD_CTL_SHIFT … #define FTDMAC020_LLI_DSTAD_CTL_MSK … #define FTDMAC020_LLI_DSTAD_CTL_SHIFT … #define FTDMAC020_LLI_SRC_SEL … #define FTDMAC020_LLI_DST_SEL … #define FTDMAC020_LLI_TRANSFER_SIZE_MASK … #define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT … #define FTDMAC020_CFG_LLP_CNT_MASK … #define FTDMAC020_CFG_LLP_CNT_SHIFT … #define FTDMAC020_CFG_BUSY … #define FTDMAC020_CFG_INT_ABT_MSK … #define FTDMAC020_CFG_INT_ERR_MSK … #define FTDMAC020_CFG_INT_TC_MSK … /* DMA linked list chain structure */ struct pl080_lli { … }; struct pl080s_lli { … }; #endif /* ASM_PL080_H */
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