// SPDX-License-Identifier: GPL-2.0 /* * SuperH Timer Support - MTU2 * * Copyright (C) 2009 Magnus Damm */ #include <linux/clk.h> #include <linux/clockchips.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/ioport.h> #include <linux/irq.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_runtime.h> #include <linux/sh_timer.h> #include <linux/slab.h> #include <linux/spinlock.h> #ifdef CONFIG_SUPERH #include <asm/platform_early.h> #endif struct sh_mtu2_device; struct sh_mtu2_channel { … }; struct sh_mtu2_device { … }; #define TSTR … #define TCR … #define TMDR … #define TIOR … #define TIER … #define TSR … #define TCNT … #define TGR … #define TCR_CCLR_NONE … #define TCR_CCLR_TGRA … #define TCR_CCLR_TGRB … #define TCR_CCLR_SYNC … #define TCR_CCLR_TGRC … #define TCR_CCLR_TGRD … #define TCR_CCLR_MASK … #define TCR_CKEG_RISING … #define TCR_CKEG_FALLING … #define TCR_CKEG_BOTH … #define TCR_CKEG_MASK … /* Values 4 to 7 are channel-dependent */ #define TCR_TPSC_P1 … #define TCR_TPSC_P4 … #define TCR_TPSC_P16 … #define TCR_TPSC_P64 … #define TCR_TPSC_CH0_TCLKA … #define TCR_TPSC_CH0_TCLKB … #define TCR_TPSC_CH0_TCLKC … #define TCR_TPSC_CH0_TCLKD … #define TCR_TPSC_CH1_TCLKA … #define TCR_TPSC_CH1_TCLKB … #define TCR_TPSC_CH1_P256 … #define TCR_TPSC_CH1_TCNT2 … #define TCR_TPSC_CH2_TCLKA … #define TCR_TPSC_CH2_TCLKB … #define TCR_TPSC_CH2_TCLKC … #define TCR_TPSC_CH2_P1024 … #define TCR_TPSC_CH34_P256 … #define TCR_TPSC_CH34_P1024 … #define TCR_TPSC_CH34_TCLKA … #define TCR_TPSC_CH34_TCLKB … #define TCR_TPSC_MASK … #define TMDR_BFE … #define TMDR_BFB … #define TMDR_BFA … #define TMDR_MD_NORMAL … #define TMDR_MD_PWM_1 … #define TMDR_MD_PWM_2 … #define TMDR_MD_PHASE_1 … #define TMDR_MD_PHASE_2 … #define TMDR_MD_PHASE_3 … #define TMDR_MD_PHASE_4 … #define TMDR_MD_PWM_SYNC … #define TMDR_MD_PWM_COMP_CREST … #define TMDR_MD_PWM_COMP_TROUGH … #define TMDR_MD_PWM_COMP_BOTH … #define TMDR_MD_MASK … #define TIOC_IOCH(n) … #define TIOC_IOCL(n) … #define TIOR_OC_RETAIN … #define TIOR_OC_0_CLEAR … #define TIOR_OC_0_SET … #define TIOR_OC_0_TOGGLE … #define TIOR_OC_1_CLEAR … #define TIOR_OC_1_SET … #define TIOR_OC_1_TOGGLE … #define TIOR_IC_RISING … #define TIOR_IC_FALLING … #define TIOR_IC_BOTH … #define TIOR_IC_TCNT … #define TIOR_MASK … #define TIER_TTGE … #define TIER_TTGE2 … #define TIER_TCIEU … #define TIER_TCIEV … #define TIER_TGIED … #define TIER_TGIEC … #define TIER_TGIEB … #define TIER_TGIEA … #define TSR_TCFD … #define TSR_TCFU … #define TSR_TCFV … #define TSR_TGFD … #define TSR_TGFC … #define TSR_TGFB … #define TSR_TGFA … static unsigned long mtu2_reg_offs[] = …; static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr) { … } static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr, unsigned long value) { … } static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start) { … } static int sh_mtu2_enable(struct sh_mtu2_channel *ch) { … } static void sh_mtu2_disable(struct sh_mtu2_channel *ch) { … } static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id) { … } static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced) { … } static int sh_mtu2_clock_event_shutdown(struct clock_event_device *ced) { … } static int sh_mtu2_clock_event_set_periodic(struct clock_event_device *ced) { … } static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced) { … } static void sh_mtu2_clock_event_resume(struct clock_event_device *ced) { … } static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch, const char *name) { … } static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name) { … } static const unsigned int sh_mtu2_channel_offsets[] = …; static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index, struct sh_mtu2_device *mtu) { … } static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu) { … } static int sh_mtu2_setup(struct sh_mtu2_device *mtu, struct platform_device *pdev) { … } static int sh_mtu2_probe(struct platform_device *pdev) { … } static const struct platform_device_id sh_mtu2_id_table[] = …; MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table); static const struct of_device_id sh_mtu2_of_table[] __maybe_unused = …; MODULE_DEVICE_TABLE(of, sh_mtu2_of_table); static struct platform_driver sh_mtu2_device_driver = …; static int __init sh_mtu2_init(void) { … } static void __exit sh_mtu2_exit(void) { … } #ifdef CONFIG_SUPERH sh_early_platform_init("earlytimer", &sh_mtu2_device_driver); #endif subsys_initcall(sh_mtu2_init); module_exit(sh_mtu2_exit); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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