// SPDX-License-Identifier: GPL-2.0 /* * SuperH Timer Support - CMT * * Copyright (C) 2008 Magnus Damm */ #include <linux/clk.h> #include <linux/clockchips.h> #include <linux/clocksource.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/ioport.h> #include <linux/irq.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_runtime.h> #include <linux/sh_timer.h> #include <linux/slab.h> #include <linux/spinlock.h> #ifdef CONFIG_SUPERH #include <asm/platform_early.h> #endif struct sh_cmt_device; /* * The CMT comes in 5 different identified flavours, depending not only on the * SoC but also on the particular instance. The following table lists the main * characteristics of those flavours. * * 16B 32B 32B-F 48B R-Car Gen2 * ----------------------------------------------------------------------------- * Channels 2 1/4 1 6 2/8 * Control Width 16 16 16 16 32 * Counter Width 16 32 32 32/48 32/48 * Shared Start/Stop Y Y Y Y N * * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register * located in the channel registers block. All other versions have a shared * start/stop register located in the global space. * * Channels are indexed from 0 to N-1 in the documentation. The channel index * infers the start/stop bit position in the control register and the channel * registers block address. Some CMT instances have a subset of channels * available, in which case the index in the documentation doesn't match the * "real" index as implemented in hardware. This is for instance the case with * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 * in the documentation but using start/stop bit 5 and having its registers * block at 0x60. * * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. */ enum sh_cmt_model { … }; struct sh_cmt_info { … }; struct sh_cmt_channel { … }; struct sh_cmt_device { … }; #define SH_CMT16_CMCSR_CMF … #define SH_CMT16_CMCSR_CMIE … #define SH_CMT16_CMCSR_CKS8 … #define SH_CMT16_CMCSR_CKS32 … #define SH_CMT16_CMCSR_CKS128 … #define SH_CMT16_CMCSR_CKS512 … #define SH_CMT16_CMCSR_CKS_MASK … #define SH_CMT32_CMCSR_CMF … #define SH_CMT32_CMCSR_OVF … #define SH_CMT32_CMCSR_WRFLG … #define SH_CMT32_CMCSR_STTF … #define SH_CMT32_CMCSR_STPF … #define SH_CMT32_CMCSR_SSIE … #define SH_CMT32_CMCSR_CMS … #define SH_CMT32_CMCSR_CMM … #define SH_CMT32_CMCSR_CMTOUT_IE … #define SH_CMT32_CMCSR_CMR_NONE … #define SH_CMT32_CMCSR_CMR_DMA … #define SH_CMT32_CMCSR_CMR_IRQ … #define SH_CMT32_CMCSR_CMR_MASK … #define SH_CMT32_CMCSR_DBGIVD … #define SH_CMT32_CMCSR_CKS_RCLK8 … #define SH_CMT32_CMCSR_CKS_RCLK32 … #define SH_CMT32_CMCSR_CKS_RCLK128 … #define SH_CMT32_CMCSR_CKS_RCLK1 … #define SH_CMT32_CMCSR_CKS_MASK … static u32 sh_cmt_read16(void __iomem *base, unsigned long offs) { … } static u32 sh_cmt_read32(void __iomem *base, unsigned long offs) { … } static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value) { … } static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value) { … } static const struct sh_cmt_info sh_cmt_info[] = …; #define CMCSR … #define CMCNT … #define CMCOR … #define CMCLKE … static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) { … } static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) { … } static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) { … } static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value) { … } static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) { … } static inline int sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value) { … } static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value) { … } static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped) { … } static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) { … } static int sh_cmt_enable(struct sh_cmt_channel *ch) { … } static void sh_cmt_disable(struct sh_cmt_channel *ch) { … } /* private flags */ #define FLAG_CLOCKEVENT … #define FLAG_CLOCKSOURCE … #define FLAG_REPROGRAM … #define FLAG_SKIPEVENT … #define FLAG_IRQCONTEXT … static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, int absolute) { … } static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) { … } static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) { … } static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) { … } static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) { … } static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) { … } static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) { … } static u64 sh_cmt_clocksource_read(struct clocksource *cs) { … } static int sh_cmt_clocksource_enable(struct clocksource *cs) { … } static void sh_cmt_clocksource_disable(struct clocksource *cs) { … } static void sh_cmt_clocksource_suspend(struct clocksource *cs) { … } static void sh_cmt_clocksource_resume(struct clocksource *cs) { … } static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, const char *name) { … } static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) { … } static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) { … } static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced) { … } static int sh_cmt_clock_event_set_state(struct clock_event_device *ced, int periodic) { … } static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced) { … } static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced) { … } static int sh_cmt_clock_event_next(unsigned long delta, struct clock_event_device *ced) { … } static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) { … } static void sh_cmt_clock_event_resume(struct clock_event_device *ced) { … } static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, const char *name) { … } static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, bool clockevent, bool clocksource) { … } static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, unsigned int hwidx, bool clockevent, bool clocksource, struct sh_cmt_device *cmt) { … } static int sh_cmt_map_memory(struct sh_cmt_device *cmt) { … } static const struct platform_device_id sh_cmt_id_table[] = …; MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); static const struct of_device_id sh_cmt_of_table[] __maybe_unused = …; MODULE_DEVICE_TABLE(of, sh_cmt_of_table); static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) { … } static int sh_cmt_probe(struct platform_device *pdev) { … } static struct platform_driver sh_cmt_device_driver = …; static int __init sh_cmt_init(void) { … } static void __exit sh_cmt_exit(void) { … } #ifdef CONFIG_SUPERH sh_early_platform_init("earlytimer", &sh_cmt_device_driver); #endif subsys_initcall(sh_cmt_init); module_exit(sh_cmt_exit); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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