// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2014 Oleksij Rempel <[email protected]> */ #include <linux/kernel.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/sched.h> #include <linux/clk.h> #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/bitops.h> #define DRIVER_NAME … /* * this device provide 4 offsets for each register: * 0x0 - plain read write mode * 0x4 - set mode, OR logic. * 0x8 - clr mode, XOR logic. * 0xc - togle mode. */ #define SET_REG … #define CLR_REG … #define HW_IR … #define BM_IR_CR0 … #define BM_IR_MR3 … #define BM_IR_MR2 … #define BM_IR_MR1 … #define BM_IR_MR0 … #define HW_TCR … /* BM_C*_RST * Timer Counter and the Prescale Counter are synchronously reset on the * next positive edge of PCLK. The counters remain reset until TCR[1] is * returned to zero. */ #define BM_C3_RST … #define BM_C2_RST … #define BM_C1_RST … #define BM_C0_RST … /* BM_C*_EN * 1 - Timer Counter and Prescale Counter are enabled for counting * 0 - counters are disabled */ #define BM_C3_EN … #define BM_C2_EN … #define BM_C1_EN … #define BM_C0_EN … #define HW_DIR … /* 00 - count up * 01 - count down * 10 - ?? 2^n/2 */ #define BM_DIR_COUNT_UP … #define BM_DIR_COUNT_DOWN … #define BM_DIR0_SHIFT … #define BM_DIR1_SHIFT … #define BM_DIR2_SHIFT … #define BM_DIR3_SHIFT … #define BM_DIR_DEFAULT … #define HW_TC0 … /* HW_TC*. Timer counter owerflow (0xffff.ffff to 0x0000.0000) do not generate * interrupt. This registers can be used to detect overflow */ #define HW_TC1 … #define HW_TC2 … #define HW_TC3 … #define HW_PR … #define BM_PR_DISABLE … #define HW_PC … #define HW_MCR … /* enable interrupt on match */ #define BM_MCR_INT_EN(n) … /* enable TC reset on match */ #define BM_MCR_RES_EN(n) … /* enable stop TC on match */ #define BM_MCR_STOP_EN(n) … #define HW_MR0 … #define HW_MR1 … #define HW_MR2 … #define HW_MR3 … #define HW_CTCR … #define BM_CTCR0_SHIFT … #define BM_CTCR1_SHIFT … #define BM_CTCR2_SHIFT … #define BM_CTCR3_SHIFT … #define BM_CTCR_TM … #define BM_CTCR_DEFAULT … static struct asm9260_timer_priv { … } priv; static int asm9260_timer_set_next_event(unsigned long delta, struct clock_event_device *evt) { … } static inline void __asm9260_timer_shutdown(struct clock_event_device *evt) { … } static int asm9260_timer_shutdown(struct clock_event_device *evt) { … } static int asm9260_timer_set_oneshot(struct clock_event_device *evt) { … } static int asm9260_timer_set_periodic(struct clock_event_device *evt) { … } static struct clock_event_device event_dev = …; static irqreturn_t asm9260_timer_interrupt(int irq, void *dev_id) { … } /* * --------------------------------------------------------------------------- * Timer initialization * --------------------------------------------------------------------------- */ static int __init asm9260_timer_init(struct device_node *np) { … } TIMER_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer", asm9260_timer_init);
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