/* SPDX-License-Identifier: GPL-2.0-only */ /* * ISH registers definitions * * Copyright (c) 2012-2016, Intel Corporation. */ #ifndef _ISHTP_ISH_REGS_H_ #define _ISHTP_ISH_REGS_H_ /*** IPC PCI Offsets and sizes ***/ /* ISH IPC Base Address */ #define IPC_REG_BASE … /* Peripheral Interrupt Status Register */ #define IPC_REG_PISR_CHV_AB … /* Peripheral Interrupt Mask Register */ #define IPC_REG_PIMR_CHV_AB … /*BXT, CHV_K0*/ /*Peripheral Interrupt Status Register */ #define IPC_REG_PISR_BXT … /*Peripheral Interrupt Mask Register */ #define IPC_REG_PIMR_BXT … /***********************************/ /* ISH Host Firmware status Register */ #define IPC_REG_ISH_HOST_FWSTS … /* Host Communication Register */ #define IPC_REG_HOST_COMM … /* Reset register */ #define IPC_REG_ISH_RST … /* Inbound doorbell register Host to ISH */ #define IPC_REG_HOST2ISH_DRBL … /* Outbound doorbell register ISH to Host */ #define IPC_REG_ISH2HOST_DRBL … /* ISH to HOST message registers */ #define IPC_REG_ISH2HOST_MSG … /* HOST to ISH message registers */ #define IPC_REG_HOST2ISH_MSG … /* REMAP2 to enable DMA (D3 RCR) */ #define IPC_REG_ISH_RMP2 … #define IPC_REG_MAX … /*** register bits - HISR ***/ /* bit corresponds HOST2ISH interrupt in PISR and PIMR registers */ #define IPC_INT_HOST2ISH_BIT … /***********************************/ /*CHV_A0, CHV_B0*/ /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */ #define IPC_INT_ISH2HOST_BIT_CHV_AB … /*BXT, CHV_K0*/ /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */ #define IPC_INT_ISH2HOST_BIT_BXT … /***********************************/ /* bit corresponds ISH2HOST busy clear interrupt in PIMR register */ #define IPC_INT_ISH2HOST_CLR_MASK_BIT … /* offset of ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */ #define IPC_INT_ISH2HOST_CLR_OFFS … /* bit corresponds ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */ #define IPC_INT_ISH2HOST_CLR_BIT … /* bit corresponds busy bit in doorbell registers */ #define IPC_DRBL_BUSY_OFFS … #define IPC_DRBL_BUSY_BIT … #define IPC_HOST_OWNS_MSG_OFFS … /* * A0: bit means that host owns MSGnn registers and is reading them. * ISH FW may not write to them */ #define IPC_HOST_OWNS_MSG_BIT … /* * Host status bits (HOSTCOMM) */ /* bit corresponds host ready bit in Host Status Register (HOST_COMM) */ #define IPC_HOSTCOMM_READY_OFFS … #define IPC_HOSTCOMM_READY_BIT … /***********************************/ /*CHV_A0, CHV_B0*/ #define IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB … #define IPC_HOSTCOMM_INT_EN_BIT_CHV_AB … /*BXT, CHV_K0*/ #define IPC_PIMR_INT_EN_OFFS_BXT … #define IPC_PIMR_INT_EN_BIT_BXT … #define IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT … #define IPC_HOST2ISH_BUSYCLEAR_MASK_BIT … /***********************************/ /* * both Host and ISH have ILUP at bit 0 * bit corresponds host ready bit in both status registers */ #define IPC_ILUP_OFFS … #define IPC_ILUP_BIT … /* * ISH FW status bits in ISH FW Status Register */ #define IPC_ISH_FWSTS_SHIFT … #define IPC_ISH_FWSTS_MASK … #define IPC_GET_ISH_FWSTS(status) … /* * FW status bits (relevant) */ #define IPC_FWSTS_ILUP … #define IPC_FWSTS_ISHTP_UP … #define IPC_FWSTS_DMA0 … #define IPC_FWSTS_DMA1 … #define IPC_FWSTS_DMA2 … #define IPC_FWSTS_DMA3 … #define IPC_ISH_IN_DMA … /* bit corresponds host ready bit in ISH FW Status Register */ #define IPC_ISH_ISHTP_READY_OFFS … #define IPC_ISH_ISHTP_READY_BIT … #define IPC_RMP2_DMA_ENABLED … #define IPC_MSG_MAX_SIZE … #define IPC_HEADER_LENGTH_MASK … #define IPC_HEADER_PROTOCOL_MASK … #define IPC_HEADER_MNG_CMD_MASK … #define IPC_HEADER_LENGTH_OFFSET … #define IPC_HEADER_PROTOCOL_OFFSET … #define IPC_HEADER_MNG_CMD_OFFSET … #define IPC_HEADER_GET_LENGTH(drbl_reg) … #define IPC_HEADER_GET_PROTOCOL(drbl_reg) … #define IPC_HEADER_GET_MNG_CMD(drbl_reg) … #define IPC_IS_BUSY(drbl_reg) … /***********************************/ /*CHV_A0, CHV_B0*/ #define IPC_INT_FROM_ISH_TO_HOST_CHV_AB(drbl_reg) … /*BXT, CHV_K0*/ #define IPC_INT_FROM_ISH_TO_HOST_BXT(drbl_reg) … /***********************************/ #define IPC_BUILD_HEADER(length, protocol, busy) … #define IPC_BUILD_MNG_MSG(cmd, length) … #define IPC_SET_HOST_READY(host_status) … #define IPC_SET_HOST_ILUP(host_status) … #define IPC_CLEAR_HOST_READY(host_status) … #define IPC_CLEAR_HOST_ILUP(host_status) … /* todo - temp until PIMR HW ready */ #define IPC_HOST_BUSY_READING_OFFS … /* bit corresponds host ready bit in Host Status Register (HOST_COMM) */ #define IPC_HOST_BUSY_READING_BIT … #define IPC_SET_HOST_BUSY_READING(host_status) … #define IPC_CLEAR_HOST_BUSY_READING(host_status) … #define IPC_IS_ISH_ISHTP_READY(ish_status) … #define IPC_IS_ISH_ILUP(ish_status) … #define IPC_PROTOCOL_ISHTP … #define IPC_PROTOCOL_MNG … #define MNG_RX_CMPL_ENABLE … #define MNG_RX_CMPL_DISABLE … #define MNG_RX_CMPL_INDICATION … #define MNG_RESET_NOTIFY … #define MNG_RESET_NOTIFY_ACK … #define MNG_SYNC_FW_CLOCK … #define MNG_ILLEGAL_CMD … #endif /* _ISHTP_ISH_REGS_H_ */
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