/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2021 MediaTek Inc. * Author: Wenzhen.Yu <[email protected]> * Author: Jianhui Zhao <[email protected]> * Author: Daniel Golle <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT7981_H #define _DT_BINDINGS_CLK_MT7981_H /* TOPCKGEN */ #define CLK_TOP_CB_CKSQ_40M … #define CLK_TOP_CB_M_416M … #define CLK_TOP_CB_M_D2 … #define CLK_TOP_CB_M_D3 … #define CLK_TOP_M_D3_D2 … #define CLK_TOP_CB_M_D4 … #define CLK_TOP_CB_M_D8 … #define CLK_TOP_M_D8_D2 … #define CLK_TOP_CB_MM_720M … #define CLK_TOP_CB_MM_D2 … #define CLK_TOP_CB_MM_D3 … #define CLK_TOP_CB_MM_D3_D5 … #define CLK_TOP_CB_MM_D4 … #define CLK_TOP_CB_MM_D6 … #define CLK_TOP_MM_D6_D2 … #define CLK_TOP_CB_MM_D8 … #define CLK_TOP_CB_APLL2_196M … #define CLK_TOP_APLL2_D2 … #define CLK_TOP_APLL2_D4 … #define CLK_TOP_NET1_2500M … #define CLK_TOP_CB_NET1_D4 … #define CLK_TOP_CB_NET1_D5 … #define CLK_TOP_NET1_D5_D2 … #define CLK_TOP_NET1_D5_D4 … #define CLK_TOP_CB_NET1_D8 … #define CLK_TOP_NET1_D8_D2 … #define CLK_TOP_NET1_D8_D4 … #define CLK_TOP_CB_NET2_800M … #define CLK_TOP_CB_NET2_D2 … #define CLK_TOP_CB_NET2_D4 … #define CLK_TOP_NET2_D4_D2 … #define CLK_TOP_NET2_D4_D4 … #define CLK_TOP_CB_NET2_D6 … #define CLK_TOP_CB_WEDMCU_208M … #define CLK_TOP_CB_SGM_325M … #define CLK_TOP_CKSQ_40M_D2 … #define CLK_TOP_CB_RTC_32K … #define CLK_TOP_CB_RTC_32P7K … #define CLK_TOP_USB_TX250M … #define CLK_TOP_FAUD … #define CLK_TOP_NFI1X … #define CLK_TOP_USB_EQ_RX250M … #define CLK_TOP_USB_CDR_CK … #define CLK_TOP_USB_LN0_CK … #define CLK_TOP_SPINFI_BCK … #define CLK_TOP_SPI … #define CLK_TOP_SPIM_MST … #define CLK_TOP_UART_BCK … #define CLK_TOP_PWM_BCK … #define CLK_TOP_I2C_BCK … #define CLK_TOP_PEXTP_TL … #define CLK_TOP_EMMC_208M … #define CLK_TOP_EMMC_400M … #define CLK_TOP_DRAMC_REF … #define CLK_TOP_DRAMC_MD32 … #define CLK_TOP_SYSAXI … #define CLK_TOP_SYSAPB … #define CLK_TOP_ARM_DB_MAIN … #define CLK_TOP_AP2CNN_HOST … #define CLK_TOP_NETSYS … #define CLK_TOP_NETSYS_500M … #define CLK_TOP_NETSYS_WED_MCU … #define CLK_TOP_NETSYS_2X … #define CLK_TOP_SGM_325M … #define CLK_TOP_SGM_REG … #define CLK_TOP_F26M … #define CLK_TOP_EIP97B … #define CLK_TOP_USB3_PHY … #define CLK_TOP_AUD … #define CLK_TOP_A1SYS … #define CLK_TOP_AUD_L … #define CLK_TOP_A_TUNER … #define CLK_TOP_U2U3_REF … #define CLK_TOP_U2U3_SYS … #define CLK_TOP_U2U3_XHCI … #define CLK_TOP_USB_FRMCNT … #define CLK_TOP_NFI1X_SEL … #define CLK_TOP_SPINFI_SEL … #define CLK_TOP_SPI_SEL … #define CLK_TOP_SPIM_MST_SEL … #define CLK_TOP_UART_SEL … #define CLK_TOP_PWM_SEL … #define CLK_TOP_I2C_SEL … #define CLK_TOP_PEXTP_TL_SEL … #define CLK_TOP_EMMC_208M_SEL … #define CLK_TOP_EMMC_400M_SEL … #define CLK_TOP_F26M_SEL … #define CLK_TOP_DRAMC_SEL … #define CLK_TOP_DRAMC_MD32_SEL … #define CLK_TOP_SYSAXI_SEL … #define CLK_TOP_SYSAPB_SEL … #define CLK_TOP_ARM_DB_MAIN_SEL … #define CLK_TOP_AP2CNN_HOST_SEL … #define CLK_TOP_NETSYS_SEL … #define CLK_TOP_NETSYS_500M_SEL … #define CLK_TOP_NETSYS_MCU_SEL … #define CLK_TOP_NETSYS_2X_SEL … #define CLK_TOP_SGM_325M_SEL … #define CLK_TOP_SGM_REG_SEL … #define CLK_TOP_EIP97B_SEL … #define CLK_TOP_USB3_PHY_SEL … #define CLK_TOP_AUD_SEL … #define CLK_TOP_A1SYS_SEL … #define CLK_TOP_AUD_L_SEL … #define CLK_TOP_A_TUNER_SEL … #define CLK_TOP_U2U3_SEL … #define CLK_TOP_U2U3_SYS_SEL … #define CLK_TOP_U2U3_XHCI_SEL … #define CLK_TOP_USB_FRMCNT_SEL … #define CLK_TOP_AUD_I2S_M … /* INFRACFG */ #define CLK_INFRA_66M_MCK … #define CLK_INFRA_UART0_SEL … #define CLK_INFRA_UART1_SEL … #define CLK_INFRA_UART2_SEL … #define CLK_INFRA_SPI0_SEL … #define CLK_INFRA_SPI1_SEL … #define CLK_INFRA_SPI2_SEL … #define CLK_INFRA_PWM1_SEL … #define CLK_INFRA_PWM2_SEL … #define CLK_INFRA_PWM3_SEL … #define CLK_INFRA_PWM_BSEL … #define CLK_INFRA_PCIE_SEL … #define CLK_INFRA_GPT_STA … #define CLK_INFRA_PWM_HCK … #define CLK_INFRA_PWM_STA … #define CLK_INFRA_PWM1_CK … #define CLK_INFRA_PWM2_CK … #define CLK_INFRA_PWM3_CK … #define CLK_INFRA_CQ_DMA_CK … #define CLK_INFRA_AUD_BUS_CK … #define CLK_INFRA_AUD_26M_CK … #define CLK_INFRA_AUD_L_CK … #define CLK_INFRA_AUD_AUD_CK … #define CLK_INFRA_AUD_EG2_CK … #define CLK_INFRA_DRAMC_26M_CK … #define CLK_INFRA_DBG_CK … #define CLK_INFRA_AP_DMA_CK … #define CLK_INFRA_SEJ_CK … #define CLK_INFRA_SEJ_13M_CK … #define CLK_INFRA_THERM_CK … #define CLK_INFRA_I2C0_CK … #define CLK_INFRA_UART0_CK … #define CLK_INFRA_UART1_CK … #define CLK_INFRA_UART2_CK … #define CLK_INFRA_SPI2_CK … #define CLK_INFRA_SPI2_HCK_CK … #define CLK_INFRA_NFI1_CK … #define CLK_INFRA_SPINFI1_CK … #define CLK_INFRA_NFI_HCK_CK … #define CLK_INFRA_SPI0_CK … #define CLK_INFRA_SPI1_CK … #define CLK_INFRA_SPI0_HCK_CK … #define CLK_INFRA_SPI1_HCK_CK … #define CLK_INFRA_FRTC_CK … #define CLK_INFRA_MSDC_CK … #define CLK_INFRA_MSDC_HCK_CK … #define CLK_INFRA_MSDC_133M_CK … #define CLK_INFRA_MSDC_66M_CK … #define CLK_INFRA_ADC_26M_CK … #define CLK_INFRA_ADC_FRC_CK … #define CLK_INFRA_FBIST2FPC_CK … #define CLK_INFRA_I2C_MCK_CK … #define CLK_INFRA_I2C_PCK_CK … #define CLK_INFRA_IUSB_133_CK … #define CLK_INFRA_IUSB_66M_CK … #define CLK_INFRA_IUSB_SYS_CK … #define CLK_INFRA_IUSB_CK … #define CLK_INFRA_IPCIE_CK … #define CLK_INFRA_IPCIE_PIPE_CK … #define CLK_INFRA_IPCIER_CK … #define CLK_INFRA_IPCIEB_CK … /* APMIXEDSYS */ #define CLK_APMIXED_ARMPLL … #define CLK_APMIXED_NET2PLL … #define CLK_APMIXED_MMPLL … #define CLK_APMIXED_SGMPLL … #define CLK_APMIXED_WEDMCUPLL … #define CLK_APMIXED_NET1PLL … #define CLK_APMIXED_MPLL … #define CLK_APMIXED_APLL2 … /* SGMIISYS_0 */ #define CLK_SGM0_TX_EN … #define CLK_SGM0_RX_EN … #define CLK_SGM0_CK0_EN … #define CLK_SGM0_CDR_CK0_EN … /* SGMIISYS_1 */ #define CLK_SGM1_TX_EN … #define CLK_SGM1_RX_EN … #define CLK_SGM1_CK1_EN … #define CLK_SGM1_CDR_CK1_EN … /* ETHSYS */ #define CLK_ETH_FE_EN … #define CLK_ETH_GP2_EN … #define CLK_ETH_GP1_EN … #define CLK_ETH_WOCPU0_EN … #endif /* _DT_BINDINGS_CLK_MT7981_H */
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