/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2023 MediaTek Inc. * Author: Sam Shih <[email protected]> * Author: Xiufeng Li <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT7988_H #define _DT_BINDINGS_CLK_MT7988_H /* APMIXEDSYS */ #define CLK_APMIXED_NETSYSPLL … #define CLK_APMIXED_MPLL … #define CLK_APMIXED_MMPLL … #define CLK_APMIXED_APLL2 … #define CLK_APMIXED_NET1PLL … #define CLK_APMIXED_NET2PLL … #define CLK_APMIXED_WEDMCUPLL … #define CLK_APMIXED_SGMPLL … #define CLK_APMIXED_ARM_B … #define CLK_APMIXED_CCIPLL2_B … #define CLK_APMIXED_USXGMIIPLL … #define CLK_APMIXED_MSDCPLL … /* TOPCKGEN */ #define CLK_TOP_XTAL … #define CLK_TOP_XTAL_D2 … #define CLK_TOP_RTC_32K … #define CLK_TOP_RTC_32P7K … #define CLK_TOP_MPLL_D2 … #define CLK_TOP_MPLL_D3_D2 … #define CLK_TOP_MPLL_D4 … #define CLK_TOP_MPLL_D8 … #define CLK_TOP_MPLL_D8_D2 … #define CLK_TOP_MMPLL_D2 … #define CLK_TOP_MMPLL_D3_D5 … #define CLK_TOP_MMPLL_D4 … #define CLK_TOP_MMPLL_D6_D2 … #define CLK_TOP_MMPLL_D8 … #define CLK_TOP_APLL2_D4 … #define CLK_TOP_NET1PLL_D4 … #define CLK_TOP_NET1PLL_D5 … #define CLK_TOP_NET1PLL_D5_D2 … #define CLK_TOP_NET1PLL_D5_D4 … #define CLK_TOP_NET1PLL_D8 … #define CLK_TOP_NET1PLL_D8_D2 … #define CLK_TOP_NET1PLL_D8_D4 … #define CLK_TOP_NET1PLL_D8_D8 … #define CLK_TOP_NET1PLL_D8_D16 … #define CLK_TOP_NET2PLL_D2 … #define CLK_TOP_NET2PLL_D4 … #define CLK_TOP_NET2PLL_D4_D4 … #define CLK_TOP_NET2PLL_D4_D8 … #define CLK_TOP_NET2PLL_D6 … #define CLK_TOP_NET2PLL_D8 … #define CLK_TOP_NETSYS_SEL … #define CLK_TOP_NETSYS_500M_SEL … #define CLK_TOP_NETSYS_2X_SEL … #define CLK_TOP_NETSYS_GSW_SEL … #define CLK_TOP_ETH_GMII_SEL … #define CLK_TOP_NETSYS_MCU_SEL … #define CLK_TOP_NETSYS_PAO_2X_SEL … #define CLK_TOP_EIP197_SEL … #define CLK_TOP_AXI_INFRA_SEL … #define CLK_TOP_UART_SEL … #define CLK_TOP_EMMC_250M_SEL … #define CLK_TOP_EMMC_400M_SEL … #define CLK_TOP_SPI_SEL … #define CLK_TOP_SPIM_MST_SEL … #define CLK_TOP_NFI1X_SEL … #define CLK_TOP_SPINFI_SEL … #define CLK_TOP_PWM_SEL … #define CLK_TOP_I2C_SEL … #define CLK_TOP_PCIE_MBIST_250M_SEL … #define CLK_TOP_PEXTP_TL_SEL … #define CLK_TOP_PEXTP_TL_P1_SEL … #define CLK_TOP_PEXTP_TL_P2_SEL … #define CLK_TOP_PEXTP_TL_P3_SEL … #define CLK_TOP_USB_SYS_SEL … #define CLK_TOP_USB_SYS_P1_SEL … #define CLK_TOP_USB_XHCI_SEL … #define CLK_TOP_USB_XHCI_P1_SEL … #define CLK_TOP_USB_FRMCNT_SEL … #define CLK_TOP_USB_FRMCNT_P1_SEL … #define CLK_TOP_AUD_SEL … #define CLK_TOP_A1SYS_SEL … #define CLK_TOP_AUD_L_SEL … #define CLK_TOP_A_TUNER_SEL … #define CLK_TOP_SSPXTP_SEL … #define CLK_TOP_USB_PHY_SEL … #define CLK_TOP_USXGMII_SBUS_0_SEL … #define CLK_TOP_USXGMII_SBUS_1_SEL … #define CLK_TOP_SGM_0_SEL … #define CLK_TOP_SGM_SBUS_0_SEL … #define CLK_TOP_SGM_1_SEL … #define CLK_TOP_SGM_SBUS_1_SEL … #define CLK_TOP_XFI_PHY_0_XTAL_SEL … #define CLK_TOP_XFI_PHY_1_XTAL_SEL … #define CLK_TOP_SYSAXI_SEL … #define CLK_TOP_SYSAPB_SEL … #define CLK_TOP_ETH_REFCK_50M_SEL … #define CLK_TOP_ETH_SYS_200M_SEL … #define CLK_TOP_ETH_SYS_SEL … #define CLK_TOP_ETH_XGMII_SEL … #define CLK_TOP_BUS_TOPS_SEL … #define CLK_TOP_NPU_TOPS_SEL … #define CLK_TOP_DRAMC_SEL … #define CLK_TOP_DRAMC_MD32_SEL … #define CLK_TOP_INFRA_F26M_SEL … #define CLK_TOP_PEXTP_P0_SEL … #define CLK_TOP_PEXTP_P1_SEL … #define CLK_TOP_PEXTP_P2_SEL … #define CLK_TOP_PEXTP_P3_SEL … #define CLK_TOP_DA_XTP_GLB_P0_SEL … #define CLK_TOP_DA_XTP_GLB_P1_SEL … #define CLK_TOP_DA_XTP_GLB_P2_SEL … #define CLK_TOP_DA_XTP_GLB_P3_SEL … #define CLK_TOP_CKM_SEL … #define CLK_TOP_DA_SEL … #define CLK_TOP_PEXTP_SEL … #define CLK_TOP_TOPS_P2_26M_SEL … #define CLK_TOP_MCUSYS_BACKUP_625M_SEL … #define CLK_TOP_NETSYS_SYNC_250M_SEL … #define CLK_TOP_MACSEC_SEL … #define CLK_TOP_NETSYS_TOPS_400M_SEL … #define CLK_TOP_NETSYS_PPEFB_250M_SEL … #define CLK_TOP_NETSYS_WARP_SEL … #define CLK_TOP_ETH_MII_SEL … #define CLK_TOP_NPU_SEL … #define CLK_TOP_AUD_I2S_M … /* MCUSYS */ #define CLK_MCU_BUS_DIV_SEL … #define CLK_MCU_ARM_DIV_SEL … /* INFRACFG_AO */ #define CLK_INFRA_MUX_UART0_SEL … #define CLK_INFRA_MUX_UART1_SEL … #define CLK_INFRA_MUX_UART2_SEL … #define CLK_INFRA_MUX_SPI0_SEL … #define CLK_INFRA_MUX_SPI1_SEL … #define CLK_INFRA_MUX_SPI2_SEL … #define CLK_INFRA_PWM_SEL … #define CLK_INFRA_PWM_CK1_SEL … #define CLK_INFRA_PWM_CK2_SEL … #define CLK_INFRA_PWM_CK3_SEL … #define CLK_INFRA_PWM_CK4_SEL … #define CLK_INFRA_PWM_CK5_SEL … #define CLK_INFRA_PWM_CK6_SEL … #define CLK_INFRA_PWM_CK7_SEL … #define CLK_INFRA_PWM_CK8_SEL … #define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL … #define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL … #define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL … #define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL … /* INFRACFG */ #define CLK_INFRA_PCIE_PERI_26M_CK_P0 … #define CLK_INFRA_PCIE_PERI_26M_CK_P1 … #define CLK_INFRA_PCIE_PERI_26M_CK_P2 … #define CLK_INFRA_PCIE_PERI_26M_CK_P3 … #define CLK_INFRA_66M_GPT_BCK … #define CLK_INFRA_66M_PWM_HCK … #define CLK_INFRA_66M_PWM_BCK … #define CLK_INFRA_66M_PWM_CK1 … #define CLK_INFRA_66M_PWM_CK2 … #define CLK_INFRA_66M_PWM_CK3 … #define CLK_INFRA_66M_PWM_CK4 … #define CLK_INFRA_66M_PWM_CK5 … #define CLK_INFRA_66M_PWM_CK6 … #define CLK_INFRA_66M_PWM_CK7 … #define CLK_INFRA_66M_PWM_CK8 … #define CLK_INFRA_133M_CQDMA_BCK … #define CLK_INFRA_66M_AUD_SLV_BCK … #define CLK_INFRA_AUD_26M … #define CLK_INFRA_AUD_L … #define CLK_INFRA_AUD_AUD … #define CLK_INFRA_AUD_EG2 … #define CLK_INFRA_DRAMC_F26M … #define CLK_INFRA_133M_DBG_ACKM … #define CLK_INFRA_66M_AP_DMA_BCK … #define CLK_INFRA_66M_SEJ_BCK … #define CLK_INFRA_PRE_CK_SEJ_F13M … #define CLK_INFRA_26M_THERM_SYSTEM … #define CLK_INFRA_I2C_BCK … #define CLK_INFRA_52M_UART0_CK … #define CLK_INFRA_52M_UART1_CK … #define CLK_INFRA_52M_UART2_CK … #define CLK_INFRA_NFI … #define CLK_INFRA_SPINFI … #define CLK_INFRA_66M_NFI_HCK … #define CLK_INFRA_104M_SPI0 … #define CLK_INFRA_104M_SPI1 … #define CLK_INFRA_104M_SPI2_BCK … #define CLK_INFRA_66M_SPI0_HCK … #define CLK_INFRA_66M_SPI1_HCK … #define CLK_INFRA_66M_SPI2_HCK … #define CLK_INFRA_66M_FLASHIF_AXI … #define CLK_INFRA_RTC … #define CLK_INFRA_26M_ADC_BCK … #define CLK_INFRA_RC_ADC … #define CLK_INFRA_MSDC400 … #define CLK_INFRA_MSDC2_HCK … #define CLK_INFRA_133M_MSDC_0_HCK … #define CLK_INFRA_66M_MSDC_0_HCK … #define CLK_INFRA_133M_CPUM_BCK … #define CLK_INFRA_BIST2FPC … #define CLK_INFRA_I2C_X16W_MCK_CK_P1 … #define CLK_INFRA_I2C_X16W_PCK_CK_P1 … #define CLK_INFRA_133M_USB_HCK … #define CLK_INFRA_133M_USB_HCK_CK_P1 … #define CLK_INFRA_66M_USB_HCK … #define CLK_INFRA_66M_USB_HCK_CK_P1 … #define CLK_INFRA_USB_SYS … #define CLK_INFRA_USB_SYS_CK_P1 … #define CLK_INFRA_USB_REF … #define CLK_INFRA_USB_CK_P1 … #define CLK_INFRA_USB_FRMCNT … #define CLK_INFRA_USB_FRMCNT_CK_P1 … #define CLK_INFRA_USB_PIPE … #define CLK_INFRA_USB_PIPE_CK_P1 … #define CLK_INFRA_USB_UTMI … #define CLK_INFRA_USB_UTMI_CK_P1 … #define CLK_INFRA_USB_XHCI … #define CLK_INFRA_USB_XHCI_CK_P1 … #define CLK_INFRA_PCIE_GFMUX_TL_P0 … #define CLK_INFRA_PCIE_GFMUX_TL_P1 … #define CLK_INFRA_PCIE_GFMUX_TL_P2 … #define CLK_INFRA_PCIE_GFMUX_TL_P3 … #define CLK_INFRA_PCIE_PIPE_P0 … #define CLK_INFRA_PCIE_PIPE_P1 … #define CLK_INFRA_PCIE_PIPE_P2 … #define CLK_INFRA_PCIE_PIPE_P3 … #define CLK_INFRA_133M_PCIE_CK_P0 … #define CLK_INFRA_133M_PCIE_CK_P1 … #define CLK_INFRA_133M_PCIE_CK_P2 … #define CLK_INFRA_133M_PCIE_CK_P3 … /* ETHDMA */ #define CLK_ETHDMA_XGP1_EN … #define CLK_ETHDMA_XGP2_EN … #define CLK_ETHDMA_XGP3_EN … #define CLK_ETHDMA_FE_EN … #define CLK_ETHDMA_GP2_EN … #define CLK_ETHDMA_GP1_EN … #define CLK_ETHDMA_GP3_EN … #define CLK_ETHDMA_ESW_EN … #define CLK_ETHDMA_CRYPT0_EN … #define CLK_ETHDMA_NR_CLK … /* SGMIISYS_0 */ #define CLK_SGM0_TX_EN … #define CLK_SGM0_RX_EN … #define CLK_SGMII0_NR_CLK … /* SGMIISYS_1 */ #define CLK_SGM1_TX_EN … #define CLK_SGM1_RX_EN … #define CLK_SGMII1_NR_CLK … /* ETHWARP */ #define CLK_ETHWARP_WOCPU2_EN … #define CLK_ETHWARP_WOCPU1_EN … #define CLK_ETHWARP_WOCPU0_EN … #define CLK_ETHWARP_NR_CLK … /* XFIPLL */ #define CLK_XFIPLL_PLL … #define CLK_XFIPLL_PLL_EN … #endif /* _DT_BINDINGS_CLK_MT7988_H */
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