/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2019 MediaTek Inc. * Copyright (c) 2019 BayLibre, SAS. * Author: James Liao <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT8516_H #define _DT_BINDINGS_CLK_MT8516_H /* APMIXEDSYS */ #define CLK_APMIXED_ARMPLL … #define CLK_APMIXED_MAINPLL … #define CLK_APMIXED_UNIVPLL … #define CLK_APMIXED_MMPLL … #define CLK_APMIXED_APLL1 … #define CLK_APMIXED_APLL2 … #define CLK_APMIXED_NR_CLK … /* INFRACFG */ #define CLK_IFR_MUX1_SEL … #define CLK_IFR_ETH_25M_SEL … #define CLK_IFR_I2C0_SEL … #define CLK_IFR_I2C1_SEL … #define CLK_IFR_I2C2_SEL … #define CLK_IFR_NR_CLK … /* TOPCKGEN */ #define CLK_TOP_CLK_NULL … #define CLK_TOP_I2S_INFRA_BCK … #define CLK_TOP_MEMPLL … #define CLK_TOP_DMPLL … #define CLK_TOP_MAINPLL_D2 … #define CLK_TOP_MAINPLL_D4 … #define CLK_TOP_MAINPLL_D8 … #define CLK_TOP_MAINPLL_D16 … #define CLK_TOP_MAINPLL_D11 … #define CLK_TOP_MAINPLL_D22 … #define CLK_TOP_MAINPLL_D3 … #define CLK_TOP_MAINPLL_D6 … #define CLK_TOP_MAINPLL_D12 … #define CLK_TOP_MAINPLL_D5 … #define CLK_TOP_MAINPLL_D10 … #define CLK_TOP_MAINPLL_D20 … #define CLK_TOP_MAINPLL_D40 … #define CLK_TOP_MAINPLL_D7 … #define CLK_TOP_MAINPLL_D14 … #define CLK_TOP_UNIVPLL_D2 … #define CLK_TOP_UNIVPLL_D4 … #define CLK_TOP_UNIVPLL_D8 … #define CLK_TOP_UNIVPLL_D16 … #define CLK_TOP_UNIVPLL_D3 … #define CLK_TOP_UNIVPLL_D6 … #define CLK_TOP_UNIVPLL_D12 … #define CLK_TOP_UNIVPLL_D24 … #define CLK_TOP_UNIVPLL_D5 … #define CLK_TOP_UNIVPLL_D20 … #define CLK_TOP_MMPLL380M … #define CLK_TOP_MMPLL_D2 … #define CLK_TOP_MMPLL_200M … #define CLK_TOP_USB_PHY48M … #define CLK_TOP_APLL1 … #define CLK_TOP_APLL1_D2 … #define CLK_TOP_APLL1_D4 … #define CLK_TOP_APLL1_D8 … #define CLK_TOP_APLL2 … #define CLK_TOP_APLL2_D2 … #define CLK_TOP_APLL2_D4 … #define CLK_TOP_APLL2_D8 … #define CLK_TOP_CLK26M … #define CLK_TOP_CLK26M_D2 … #define CLK_TOP_AHB_INFRA_D2 … #define CLK_TOP_NFI1X … #define CLK_TOP_ETH_D2 … #define CLK_TOP_THEM … #define CLK_TOP_APDMA … #define CLK_TOP_I2C0 … #define CLK_TOP_I2C1 … #define CLK_TOP_AUXADC1 … #define CLK_TOP_NFI … #define CLK_TOP_NFIECC … #define CLK_TOP_DEBUGSYS … #define CLK_TOP_PWM … #define CLK_TOP_UART0 … #define CLK_TOP_UART1 … #define CLK_TOP_BTIF … #define CLK_TOP_USB … #define CLK_TOP_FLASHIF_26M … #define CLK_TOP_AUXADC2 … #define CLK_TOP_I2C2 … #define CLK_TOP_MSDC0 … #define CLK_TOP_MSDC1 … #define CLK_TOP_NFI2X … #define CLK_TOP_PMICWRAP_AP … #define CLK_TOP_SEJ … #define CLK_TOP_MEMSLP_DLYER … #define CLK_TOP_SPI … #define CLK_TOP_APXGPT … #define CLK_TOP_AUDIO … #define CLK_TOP_PMICWRAP_MD … #define CLK_TOP_PMICWRAP_CONN … #define CLK_TOP_PMICWRAP_26M … #define CLK_TOP_AUX_ADC … #define CLK_TOP_AUX_TP … #define CLK_TOP_MSDC2 … #define CLK_TOP_RBIST … #define CLK_TOP_NFI_BUS … #define CLK_TOP_GCE … #define CLK_TOP_TRNG … #define CLK_TOP_SEJ_13M … #define CLK_TOP_AES … #define CLK_TOP_PWM_B … #define CLK_TOP_PWM1_FB … #define CLK_TOP_PWM2_FB … #define CLK_TOP_PWM3_FB … #define CLK_TOP_PWM4_FB … #define CLK_TOP_PWM5_FB … #define CLK_TOP_USB_1P … #define CLK_TOP_FLASHIF_FREERUN … #define CLK_TOP_66M_ETH … #define CLK_TOP_133M_ETH … #define CLK_TOP_FETH_25M … #define CLK_TOP_FETH_50M … #define CLK_TOP_FLASHIF_AXI … #define CLK_TOP_USBIF … #define CLK_TOP_UART2 … #define CLK_TOP_BSI … #define CLK_TOP_RG_SPINOR … #define CLK_TOP_RG_MSDC2 … #define CLK_TOP_RG_ETH … #define CLK_TOP_RG_AUD1 … #define CLK_TOP_RG_AUD2 … #define CLK_TOP_RG_AUD_ENGEN1 … #define CLK_TOP_RG_AUD_ENGEN2 … #define CLK_TOP_RG_I2C … #define CLK_TOP_RG_PWM_INFRA … #define CLK_TOP_RG_AUD_SPDIF_IN … #define CLK_TOP_RG_UART2 … #define CLK_TOP_RG_BSI … #define CLK_TOP_RG_DBG_ATCLK … #define CLK_TOP_RG_NFIECC … #define CLK_TOP_RG_APLL1_D2_EN … #define CLK_TOP_RG_APLL1_D4_EN … #define CLK_TOP_RG_APLL1_D8_EN … #define CLK_TOP_RG_APLL2_D2_EN … #define CLK_TOP_RG_APLL2_D4_EN … #define CLK_TOP_RG_APLL2_D8_EN … #define CLK_TOP_APLL12_DIV0 … #define CLK_TOP_APLL12_DIV1 … #define CLK_TOP_APLL12_DIV2 … #define CLK_TOP_APLL12_DIV3 … #define CLK_TOP_APLL12_DIV4 … #define CLK_TOP_APLL12_DIV4B … #define CLK_TOP_APLL12_DIV5 … #define CLK_TOP_APLL12_DIV5B … #define CLK_TOP_APLL12_DIV6 … #define CLK_TOP_UART0_SEL … #define CLK_TOP_EMI_DDRPHY_SEL … #define CLK_TOP_AHB_INFRA_SEL … #define CLK_TOP_MSDC0_SEL … #define CLK_TOP_UART1_SEL … #define CLK_TOP_MSDC1_SEL … #define CLK_TOP_PMICSPI_SEL … #define CLK_TOP_QAXI_AUD26M_SEL … #define CLK_TOP_AUD_INTBUS_SEL … #define CLK_TOP_NFI2X_PAD_SEL … #define CLK_TOP_NFI1X_PAD_SEL … #define CLK_TOP_DDRPHYCFG_SEL … #define CLK_TOP_USB_78M_SEL … #define CLK_TOP_SPINOR_SEL … #define CLK_TOP_MSDC2_SEL … #define CLK_TOP_ETH_SEL … #define CLK_TOP_AUD1_SEL … #define CLK_TOP_AUD2_SEL … #define CLK_TOP_AUD_ENGEN1_SEL … #define CLK_TOP_AUD_ENGEN2_SEL … #define CLK_TOP_I2C_SEL … #define CLK_TOP_AUD_I2S0_M_SEL … #define CLK_TOP_AUD_I2S1_M_SEL … #define CLK_TOP_AUD_I2S2_M_SEL … #define CLK_TOP_AUD_I2S3_M_SEL … #define CLK_TOP_AUD_I2S4_M_SEL … #define CLK_TOP_AUD_I2S5_M_SEL … #define CLK_TOP_AUD_SPDIF_B_SEL … #define CLK_TOP_PWM_SEL … #define CLK_TOP_SPI_SEL … #define CLK_TOP_AUD_SPDIFIN_SEL … #define CLK_TOP_UART2_SEL … #define CLK_TOP_BSI_SEL … #define CLK_TOP_DBG_ATCLK_SEL … #define CLK_TOP_CSW_NFIECC_SEL … #define CLK_TOP_NFIECC_SEL … #define CLK_TOP_APLL12_CK_DIV0 … #define CLK_TOP_APLL12_CK_DIV1 … #define CLK_TOP_APLL12_CK_DIV2 … #define CLK_TOP_APLL12_CK_DIV3 … #define CLK_TOP_APLL12_CK_DIV4 … #define CLK_TOP_APLL12_CK_DIV4B … #define CLK_TOP_APLL12_CK_DIV5 … #define CLK_TOP_APLL12_CK_DIV5B … #define CLK_TOP_APLL12_CK_DIV6 … #define CLK_TOP_USB_78M … #define CLK_TOP_MSDC0_INFRA … #define CLK_TOP_MSDC1_INFRA … #define CLK_TOP_MSDC2_INFRA … #define CLK_TOP_NR_CLK … /* AUDSYS */ #define CLK_AUD_AFE … #define CLK_AUD_I2S … #define CLK_AUD_22M … #define CLK_AUD_24M … #define CLK_AUD_INTDIR … #define CLK_AUD_APLL2_TUNER … #define CLK_AUD_APLL_TUNER … #define CLK_AUD_HDMI … #define CLK_AUD_SPDF … #define CLK_AUD_ADC … #define CLK_AUD_DAC … #define CLK_AUD_DAC_PREDIS … #define CLK_AUD_TML … #define CLK_AUD_NR_CLK … #endif /* _DT_BINDINGS_CLK_MT8516_H */
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