/* SPDX-License-Identifier: GPL-2.0 */ /* * Z8536 CIO Internal registers */ #ifndef _Z8536_H #define _Z8536_H /* Master Interrupt Control register */ #define Z8536_INT_CTRL_REG … #define Z8536_INT_CTRL_MIE … #define Z8536_INT_CTRL_DLC … #define Z8536_INT_CTRL_NV … #define Z8536_INT_CTRL_PA_VIS … #define Z8536_INT_CTRL_PB_VIS … #define Z8536_INT_CTRL_VT_VIS … #define Z8536_INT_CTRL_RJA … #define Z8536_INT_CTRL_RESET … /* Master Configuration Control register */ #define Z8536_CFG_CTRL_REG … #define Z8536_CFG_CTRL_PBE … #define Z8536_CFG_CTRL_CT1E … #define Z8536_CFG_CTRL_CT2E … #define Z8536_CFG_CTRL_PCE_CT3E … #define Z8536_CFG_CTRL_PLC … #define Z8536_CFG_CTRL_PAE … #define Z8536_CFG_CTRL_LC(x) … #define Z8536_CFG_CTRL_LC_INDEP … #define Z8536_CFG_CTRL_LC_GATE … #define Z8536_CFG_CTRL_LC_TRIG … #define Z8536_CFG_CTRL_LC_CLK … #define Z8536_CFG_CTRL_LC_MASK … /* Interrupt Vector registers */ #define Z8536_PA_INT_VECT_REG … #define Z8536_PB_INT_VECT_REG … #define Z8536_CT_INT_VECT_REG … #define Z8536_CURR_INT_VECT_REG … /* Port A/B & Counter/Timer 1/2/3 Command and Status registers */ #define Z8536_PA_CMDSTAT_REG … #define Z8536_PB_CMDSTAT_REG … #define Z8536_CT1_CMDSTAT_REG … #define Z8536_CT2_CMDSTAT_REG … #define Z8536_CT3_CMDSTAT_REG … #define Z8536_CT_CMDSTAT_REG(x) … #define Z8536_CMD(x) … #define Z8536_CMD_NULL … #define Z8536_CMD_CLR_IP_IUS … #define Z8536_CMD_SET_IUS … #define Z8536_CMD_CLR_IUS … #define Z8536_CMD_SET_IP … #define Z8536_CMD_CLR_IP … #define Z8536_CMD_SET_IE … #define Z8536_CMD_CLR_IE … #define Z8536_CMD_MASK … #define Z8536_STAT_IUS … #define Z8536_STAT_IE … #define Z8536_STAT_IP … #define Z8536_STAT_ERR … #define Z8536_STAT_IE_IP … #define Z8536_PAB_STAT_ORE … #define Z8536_PAB_STAT_IRF … #define Z8536_PAB_STAT_PMF … #define Z8536_PAB_CMDSTAT_IOE … #define Z8536_CT_CMD_RCC … #define Z8536_CT_CMDSTAT_GCB … #define Z8536_CT_CMD_TCB … #define Z8536_CT_STAT_CIP … /* Port Data registers */ #define Z8536_PA_DATA_REG … #define Z8536_PB_DATA_REG … #define Z8536_PC_DATA_REG … /* Counter/Timer 1/2/3 Current Count registers */ #define Z8536_CT1_VAL_MSB_REG … #define Z8536_CT1_VAL_LSB_REG … #define Z8536_CT2_VAL_MSB_REG … #define Z8536_CT2_VAL_LSB_REG … #define Z8536_CT3_VAL_MSB_REG … #define Z8536_CT3_VAL_LSB_REG … #define Z8536_CT_VAL_MSB_REG(x) … #define Z8536_CT_VAL_LSB_REG(x) … /* Counter/Timer 1/2/3 Time Constant registers */ #define Z8536_CT1_RELOAD_MSB_REG … #define Z8536_CT1_RELOAD_LSB_REG … #define Z8536_CT2_RELOAD_MSB_REG … #define Z8536_CT2_RELOAD_LSB_REG … #define Z8536_CT3_RELOAD_MSB_REG … #define Z8536_CT3_RELOAD_LSB_REG … #define Z8536_CT_RELOAD_MSB_REG(x) … #define Z8536_CT_RELOAD_LSB_REG(x) … /* Counter/Timer 1/2/3 Mode Specification registers */ #define Z8536_CT1_MODE_REG … #define Z8536_CT2_MODE_REG … #define Z8536_CT3_MODE_REG … #define Z8536_CT_MODE_REG(x) … #define Z8536_CT_MODE_CSC … #define Z8536_CT_MODE_EOE … #define Z8536_CT_MODE_ECE … #define Z8536_CT_MODE_ETE … #define Z8536_CT_MODE_EGE … #define Z8536_CT_MODE_REB … #define Z8536_CT_MODE_DCS(x) … #define Z8536_CT_MODE_DCS_PULSE … #define Z8536_CT_MODE_DCS_ONESHOT … #define Z8536_CT_MODE_DCS_SQRWAVE … #define Z8536_CT_MODE_DCS_DO_NOT_USE … #define Z8536_CT_MODE_DCS_MASK … /* Port A/B Mode Specification registers */ #define Z8536_PA_MODE_REG … #define Z8536_PB_MODE_REG … #define Z8536_PAB_MODE_PTS(x) … #define Z8536_PAB_MODE_PTS_BIT … #define Z8536_PAB_MODE_PTS_INPUT … #define Z8536_PAB_MODE_PTS_OUTPUT … #define Z8536_PAB_MODE_PTS_BIDIR … #define Z8536_PAB_MODE_PTS_MASK … #define Z8536_PAB_MODE_ITB … #define Z8536_PAB_MODE_SB … #define Z8536_PAB_MODE_IMO … #define Z8536_PAB_MODE_PMS(x) … #define Z8536_PAB_MODE_PMS_DISABLE … #define Z8536_PAB_MODE_PMS_AND … #define Z8536_PAB_MODE_PMS_OR … #define Z8536_PAB_MODE_PMS_OR_PEV … #define Z8536_PAB_MODE_PMS_MASK … #define Z8536_PAB_MODE_LPM … #define Z8536_PAB_MODE_DTE … /* Port A/B Handshake Specification registers */ #define Z8536_PA_HANDSHAKE_REG … #define Z8536_PB_HANDSHAKE_REG … #define Z8536_PAB_HANDSHAKE_HST(x) … #define Z8536_PAB_HANDSHAKE_HST_INTER … #define Z8536_PAB_HANDSHAKE_HST_STROBED … #define Z8536_PAB_HANDSHAKE_HST_PULSED … #define Z8536_PAB_HANDSHAKE_HST_3WIRE … #define Z8536_PAB_HANDSHAKE_HST_MASK … #define Z8536_PAB_HANDSHAKE_RWS(x) … #define Z8536_PAB_HANDSHAKE_RWS_DISABLE … #define Z8536_PAB_HANDSHAKE_RWS_OUTWAIT … #define Z8536_PAB_HANDSHAKE_RWS_INWAIT … #define Z8536_PAB_HANDSHAKE_RWS_SPREQ … #define Z8536_PAB_HANDSHAKE_RWS_OUTREQ … #define Z8536_PAB_HANDSHAKE_RWS_INREQ … #define Z8536_PAB_HANDSHAKE_RWS_MASK … #define Z8536_PAB_HANDSHAKE_DESKEW(x) … #define Z8536_PAB_HANDSHAKE_DESKEW_MASK … /* * Port A/B/C Data Path Polarity registers * * 0 = Non-Inverting * 1 = Inverting */ #define Z8536_PA_DPP_REG … #define Z8536_PB_DPP_REG … #define Z8536_PC_DPP_REG … /* * Port A/B/C Data Direction registers * * 0 = Output bit * 1 = Input bit */ #define Z8536_PA_DD_REG … #define Z8536_PB_DD_REG … #define Z8536_PC_DD_REG … /* * Port A/B/C Special I/O Control registers * * 0 = Normal Input or Output * 1 = Output with open drain or Input with 1's catcher */ #define Z8536_PA_SIO_REG … #define Z8536_PB_SIO_REG … #define Z8536_PC_SIO_REG … /* * Port A/B Pattern Polarity/Transition/Mask registers * * PM PT PP Pattern Specification * -- -- -- ------------------------------------- * 0 0 x Bit masked off * 0 1 x Any transition * 1 0 0 Zero (low-level) * 1 0 1 One (high-level) * 1 1 0 One-to-zero transition (falling-edge) * 1 1 1 Zero-to-one transition (rising-edge) */ #define Z8536_PA_PP_REG … #define Z8536_PB_PP_REG … #define Z8536_PA_PT_REG … #define Z8536_PB_PT_REG … #define Z8536_PA_PM_REG … #define Z8536_PB_PM_REG … #endif /* _Z8536_H */
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