/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2020 MediaTek Inc. * Copyright (c) 2020 BayLibre, SAS. * Author: James Liao <[email protected]> * Fabien Parent <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT8167_H #define _DT_BINDINGS_CLK_MT8167_H /* MT8167 is based on MT8516 */ #include <dt-bindings/clock/mt8516-clk.h> /* APMIXEDSYS */ #define CLK_APMIXED_TVDPLL … #define CLK_APMIXED_LVDSPLL … #define CLK_APMIXED_HDMI_REF … #define MT8167_CLK_APMIXED_NR_CLK … /* TOPCKGEN */ #define CLK_TOP_DSI0_LNTC_DSICK … #define CLK_TOP_VPLL_DPIX … #define CLK_TOP_LVDSTX_CLKDIG_CTS … #define CLK_TOP_HDMTX_CLKDIG_CTS … #define CLK_TOP_LVDSPLL … #define CLK_TOP_LVDSPLL_D2 … #define CLK_TOP_LVDSPLL_D4 … #define CLK_TOP_LVDSPLL_D8 … #define CLK_TOP_MIPI_26M … #define CLK_TOP_TVDPLL … #define CLK_TOP_TVDPLL_D2 … #define CLK_TOP_TVDPLL_D4 … #define CLK_TOP_TVDPLL_D8 … #define CLK_TOP_TVDPLL_D16 … #define CLK_TOP_PWM_MM … #define CLK_TOP_CAM_MM … #define CLK_TOP_MFG_MM … #define CLK_TOP_SPM_52M … #define CLK_TOP_MIPI_26M_DBG … #define CLK_TOP_SCAM_MM … #define CLK_TOP_SMI_MM … #define CLK_TOP_26M_HDMI_SIFM … #define CLK_TOP_26M_CEC … #define CLK_TOP_32K_CEC … #define CLK_TOP_GCPU_B … #define CLK_TOP_RG_VDEC … #define CLK_TOP_RG_FDPI0 … #define CLK_TOP_RG_FDPI1 … #define CLK_TOP_RG_AXI_MFG … #define CLK_TOP_RG_SLOW_MFG … #define CLK_TOP_GFMUX_EMI1X_SEL … #define CLK_TOP_CSW_MUX_MFG_SEL … #define CLK_TOP_CAMTG_MM_SEL … #define CLK_TOP_PWM_MM_SEL … #define CLK_TOP_SPM_52M_SEL … #define CLK_TOP_MFG_MM_SEL … #define CLK_TOP_SMI_MM_SEL … #define CLK_TOP_SCAM_MM_SEL … #define CLK_TOP_VDEC_MM_SEL … #define CLK_TOP_DPI0_MM_SEL … #define CLK_TOP_DPI1_MM_SEL … #define CLK_TOP_AXI_MFG_IN_SEL … #define CLK_TOP_SLOW_MFG_SEL … #define MT8167_CLK_TOP_NR_CLK … /* MFGCFG */ #define CLK_MFG_BAXI … #define CLK_MFG_BMEM … #define CLK_MFG_BG3D … #define CLK_MFG_B26M … #define CLK_MFG_NR_CLK … /* MMSYS */ #define CLK_MM_SMI_COMMON … #define CLK_MM_SMI_LARB0 … #define CLK_MM_CAM_MDP … #define CLK_MM_MDP_RDMA … #define CLK_MM_MDP_RSZ0 … #define CLK_MM_MDP_RSZ1 … #define CLK_MM_MDP_TDSHP … #define CLK_MM_MDP_WDMA … #define CLK_MM_MDP_WROT … #define CLK_MM_FAKE_ENG … #define CLK_MM_DISP_OVL0 … #define CLK_MM_DISP_RDMA0 … #define CLK_MM_DISP_RDMA1 … #define CLK_MM_DISP_WDMA … #define CLK_MM_DISP_COLOR … #define CLK_MM_DISP_CCORR … #define CLK_MM_DISP_AAL … #define CLK_MM_DISP_GAMMA … #define CLK_MM_DISP_DITHER … #define CLK_MM_DISP_UFOE … #define CLK_MM_DISP_PWM_MM … #define CLK_MM_DISP_PWM_26M … #define CLK_MM_DSI_ENGINE … #define CLK_MM_DSI_DIGITAL … #define CLK_MM_DPI0_ENGINE … #define CLK_MM_DPI0_PXL … #define CLK_MM_LVDS_PXL … #define CLK_MM_LVDS_CTS … #define CLK_MM_DPI1_ENGINE … #define CLK_MM_DPI1_PXL … #define CLK_MM_HDMI_PXL … #define CLK_MM_HDMI_SPDIF … #define CLK_MM_HDMI_ADSP_BCK … #define CLK_MM_HDMI_PLL … #define CLK_MM_NR_CLK … /* IMGSYS */ #define CLK_IMG_LARB1_SMI … #define CLK_IMG_CAM_SMI … #define CLK_IMG_CAM_CAM … #define CLK_IMG_SEN_TG … #define CLK_IMG_SEN_CAM … #define CLK_IMG_VENC … #define CLK_IMG_NR_CLK … /* VDECSYS */ #define CLK_VDEC_CKEN … #define CLK_VDEC_LARB1_CKEN … #define CLK_VDEC_NR_CLK … #endif /* _DT_BINDINGS_CLK_MT8167_H */
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