/* SPDX-License-Identifier: GPL-2.0 */ /* * Support for Intel Camera Imaging ISP subsystem. * Copyright (c) 2015, Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ #ifndef _input_system_defs_h #define _input_system_defs_h /* csi controller modes */ #define HIVE_CSI_CONFIG_MAIN … #define HIVE_CSI_CONFIG_STEREO1 … #define HIVE_CSI_CONFIG_STEREO2 … /* general purpose register IDs */ /* Stream Multicast select modes */ #define HIVE_ISYS_GPREG_MULTICAST_A_IDX … #define HIVE_ISYS_GPREG_MULTICAST_B_IDX … #define HIVE_ISYS_GPREG_MULTICAST_C_IDX … /* Stream Mux select modes */ #define HIVE_ISYS_GPREG_MUX_IDX … /* streaming monitor status and control */ #define HIVE_ISYS_GPREG_STRMON_STAT_IDX … #define HIVE_ISYS_GPREG_STRMON_COND_IDX … #define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX … #define HIVE_ISYS_GPREG_SRST_IDX … #define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX … #define HIVE_ISYS_GPREG_REG_PORT_A_IDX … #define HIVE_ISYS_GPREG_REG_PORT_B_IDX … /* Bit numbers of the soft reset register */ #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT … #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT … #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT … #define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT … #define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT … #define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT … #define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT … #define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT … #define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT … #define HIVE_ISYS_GPREG_SRST_ACQ_BIT … /* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */ #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT … #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT … #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT … #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT … #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT … #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT … /* -- */ #define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT … #define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT … #define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT … #define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT … #define HIVE_ISYS_GPREG_SRST_DMA_BIT … #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT … #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT … #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT … #define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT … #define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT … #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT … #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT … #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT … #define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT … #define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT … #define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT … /* streaming monitor port id's */ #define HIVE_ISYS_STR_MON_PORT_CAPA … #define HIVE_ISYS_STR_MON_PORT_CAPB … #define HIVE_ISYS_STR_MON_PORT_CAPC … #define HIVE_ISYS_STR_MON_PORT_ACQ … #define HIVE_ISYS_STR_MON_PORT_CSS_GENSH … #define HIVE_ISYS_STR_MON_PORT_SF_GENSH … #define HIVE_ISYS_STR_MON_PORT_SP2ISYS … #define HIVE_ISYS_STR_MON_PORT_ISYS2SP … #define HIVE_ISYS_STR_MON_PORT_PIXA … #define HIVE_ISYS_STR_MON_PORT_PIXB … /* interrupt bit ID's */ #define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID … #define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID … #define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID … #define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID … #define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID … #define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID … #define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP … #define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP … /*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/ #define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP … #define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP … /*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/ #define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP … #define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP … /*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/ #define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH … /*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/ #define HIVE_ISYS_IRQ_INP_CTRL_CAPA … #define HIVE_ISYS_IRQ_INP_CTRL_CAPB … #define HIVE_ISYS_IRQ_INP_CTRL_CAPC … #define HIVE_ISYS_IRQ_CIO2AHB … #define HIVE_ISYS_IRQ_DMA_BIT_ID … #define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID … #define HIVE_ISYS_IRQ_NUM_BITS … /* DMA */ #define HIVE_ISYS_DMA_CHANNEL … #define HIVE_ISYS_DMA_IBUF_DDR_CONN … #define HIVE_ISYS_DMA_HEIGHT … #define HIVE_ISYS_DMA_ELEMS … #define HIVE_ISYS_DMA_STRIDE … #define HIVE_ISYS_DMA_CROP … #define HIVE_ISYS_DMA_EXTENSION … #endif /* _input_system_defs_h */
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