/* SPDX-License-Identifier: GPL-2.0 */ /* * Support for Medifield PNW Camera Imaging ISP subsystem. * * Copyright (c) 2012 Intel Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License version * 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * */ #ifndef ATOMISP_REGS_H #define ATOMISP_REGS_H /* common register definitions */ #define PCICMDSTS … #define INTR … #define MSI_CAPID … #define MSI_ADDRESS … #define MSI_DATA … #define INTR_CTL … #define PCI_MSI_CAPID … #define PCI_MSI_ADDR … #define PCI_MSI_DATA … #define PCI_INTERRUPT_CTRL … #define PCI_I_CONTROL … /* MRFLD specific register definitions */ #define MRFLD_CSI_AFE … #define MRFLD_CSI_CONTROL … #define MRFLD_CSI_RCOMP … #define MRFLD_PCI_PMCS … #define MRFLD_PCI_CSI_ACCESS_CTRL_VIOL … #define MRFLD_PCI_CSI_AFE_HS_CONTROL … #define MRFLD_PCI_CSI_AFE_RCOMP_CONTROL … #define MRFLD_PCI_CSI_CONTROL … #define MRFLD_PCI_CSI_AFE_TRIM_CONTROL … #define MRFLD_PCI_CSI_DEADLINE_CONTROL … #define MRFLD_PCI_CSI_RCOMP_CONTROL … /* Select Arasan (legacy)/Intel input system */ #define MRFLD_PCI_CSI_CONTROL_PARPATHEN … /* Enable CSI interface (ANN B0/K0) */ #define MRFLD_PCI_CSI_CONTROL_CSI_READY … /* * Enables the combining of adjacent 32-byte read requests to the same * cache line. When cleared, each 32-byte read request is sent as a * separate request on the IB interface. */ #define MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING … /* * Register: MRFLD_PCI_CSI_RCOMP_CONTROL * If cleared, the high speed clock going to the digital logic is gated when * RCOMP update is happening. The clock is gated for a minimum of 100 nsec. * If this bit is set, then the high speed clock is not gated during the * update cycle. */ #define MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE … /* * Enables the combining of adjacent 32-byte write requests to the same * cache line. When cleared, each 32-byte write request is sent as a * separate request on the IB interface. */ #define MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING … #define MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK … #define MRFLD_PCI_CSI1_HSRXCLKTRIM … #define MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT … #define MRFLD_PCI_CSI2_HSRXCLKTRIM … #define MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT … #define MRFLD_PCI_CSI3_HSRXCLKTRIM … #define MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT … #define MRFLD_PCI_CSI_HSRXCLKTRIM_MASK … /* * This register is IUINT MMIO register, it is used to select the CSI * receiver backend. * 1: SH CSI backend * 0: Arasan CSI backend */ #define MRFLD_CSI_RECEIVER_SELECTION_REG … #define MRFLD_INTR_CLEAR_REG … #define MRFLD_INTR_STATUS_REG … #define MRFLD_INTR_ENABLE_REG … #define MRFLD_MAX_ZOOM_FACTOR … /* MRFLD ISP POWER related */ #define MRFLD_ISPSSPM0 … #define MRFLD_ISPSSPM0_ISPSSC_OFFSET … #define MRFLD_ISPSSPM0_ISPSSS_OFFSET … #define MRFLD_ISPSSPM0_ISPSSC_MASK … #define MRFLD_ISPSSPM0_IUNIT_POWER_ON … #define MRFLD_ISPSSPM0_IUNIT_POWER_OFF … #define MRFLD_ISPSSDVFS … #define MRFLD_BIT0 … #define MRFLD_BIT1 … /* MRFLD CSI lane configuration related */ #define MRFLD_PORT_CONFIG_NUM … #define MRFLD_PORT1_ENABLE_SHIFT … #define MRFLD_PORT2_ENABLE_SHIFT … #define MRFLD_PORT3_ENABLE_SHIFT … #define MRFLD_PORT1_LANES_SHIFT … #define MRFLD_PORT2_LANES_SHIFT … #define MRFLD_PORT3_LANES_SHIFT … #define MRFLD_PORT_CONFIG_MASK … #define MRFLD_PORT_CONFIGCODE_SHIFT … #define MRFLD_ALL_CSI_PORTS_OFF_MASK … #define CHV_PORT3_LANES_SHIFT … #define CHV_PORT_CONFIG_MASK … #define ISPSSPM1 … #define ISP_FREQ_STAT_MASK … #define ISP_REQ_FREQ_MASK … #define ISP_FREQ_VALID_MASK … #define ISP_FREQ_STAT_OFFSET … #define ISP_REQ_GUAR_FREQ_OFFSET … #define ISP_REQ_FREQ_OFFSET … #define ISP_FREQ_VALID_OFFSET … #define ISP_FREQ_RULE_ANY … #define ISP_FREQ_457MHZ … #define ISP_FREQ_400MHZ … #define ISP_FREQ_356MHZ … #define ISP_FREQ_320MHZ … #define ISP_FREQ_266MHZ … #define ISP_FREQ_200MHZ … #define ISP_FREQ_100MHZ … #define HPLL_FREQ_800MHZ … #define HPLL_FREQ_1600MHZ … #define HPLL_FREQ_2000MHZ … #define CCK_FUSE_REG_0 … #define CCK_FUSE_HPLL_FREQ_MASK … /* ISP2401 CSI2+ receiver delay settings */ #define CSI2_PORT_A_BASE … #define CSI2_PORT_B_BASE … #define CSI2_PORT_C_BASE … #define CSI2_LANE_CL_BASE … #define CSI2_LANE_D0_BASE … #define CSI2_LANE_D1_BASE … #define CSI2_LANE_D2_BASE … #define CSI2_LANE_D3_BASE … #define CSI2_REG_RX_CSI_DLY_CNT_TERMEN … #define CSI2_REG_RX_CSI_DLY_CNT_SETTLE … #define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_CLANE … #define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_CLANE … #define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE0 … #define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE0 … #define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE1 … #define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE1 … #define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE2 … #define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE2 … #define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE3 … #define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE3 … #define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_CLANE … #define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_CLANE … #define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE0 … #define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE0 … #define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE1 … #define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE1 … #define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_CLANE … #define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_CLANE … #define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE0 … #define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE0 … #define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE1 … #define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE1 … #define DMA_BURST_SIZE_REG … #define ISP_DFS_TRY_TIMES … #endif /* ATOMISP_REGS_H */
Codebase Browser
linux