/* SPDX-License-Identifier: GPL-2.0 */ /* * Support for Intel Camera Imaging ISP subsystem. * Copyright (c) 2015, Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ #ifndef _dma_v2_defs_h #define _dma_v2_defs_h #define _DMA_V2_NUM_CHANNELS_ID … #define _DMA_V2_CONNECTIONS_ID … #define _DMA_V2_DEV_ELEM_WIDTHS_ID … #define _DMA_V2_DEV_FIFO_DEPTH_ID … #define _DMA_V2_DEV_FIFO_RD_LAT_ID … #define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID … #define _DMA_V2_DEV_NO_BURST_ID … #define _DMA_V2_DEV_RD_ACCEPT_ID … #define _DMA_V2_DEV_SRMD_ID … #define _DMA_V2_DEV_HAS_CRUN_ID … #define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID … #define _DMA_V2_CMD_FIFO_DEPTH_ID … #define _DMA_V2_CMD_FIFO_RD_LAT_ID … #define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID … #define _DMA_V2_NO_PACK_ID … #define _DMA_V2_REG_ALIGN … #define _DMA_V2_REG_ADDR_BITS … /* Command word */ #define _DMA_V2_CMD_IDX … #define _DMA_V2_CMD_BITS … #define _DMA_V2_CHANNEL_IDX … #define _DMA_V2_CHANNEL_BITS … /* The command to set a parameter contains the PARAM field next */ #define _DMA_V2_PARAM_IDX … #define _DMA_V2_PARAM_BITS … /* Commands to read, write or init specific blocks contain these three values */ #define _DMA_V2_SPEC_DEV_A_XB_IDX … #define _DMA_V2_SPEC_DEV_A_XB_BITS … #define _DMA_V2_SPEC_DEV_B_XB_IDX … #define _DMA_V2_SPEC_DEV_B_XB_BITS … #define _DMA_V2_SPEC_YB_IDX … #define _DMA_V2_SPEC_YB_BITS … /* */ #define _DMA_V2_CMD_CTRL_IDX … #define _DMA_V2_CMD_CTRL_BITS … /* Packing setup word */ #define _DMA_V2_CONNECTION_IDX … #define _DMA_V2_CONNECTION_BITS … #define _DMA_V2_EXTENSION_IDX … #define _DMA_V2_EXTENSION_BITS … /* Elements packing word */ #define _DMA_V2_ELEMENTS_IDX … #define _DMA_V2_ELEMENTS_BITS … #define _DMA_V2_LEFT_CROPPING_IDX … #define _DMA_V2_LEFT_CROPPING_BITS … #define _DMA_V2_WIDTH_IDX … #define _DMA_V2_WIDTH_BITS … #define _DMA_V2_HEIGHT_IDX … #define _DMA_V2_HEIGHT_BITS … #define _DMA_V2_STRIDE_IDX … #define _DMA_V2_STRIDE_BITS … /* Command IDs */ #define _DMA_V2_MOVE_B2A_COMMAND … #define _DMA_V2_MOVE_B2A_BLOCK_COMMAND … #define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND … #define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND … #define _DMA_V2_MOVE_A2B_COMMAND … #define _DMA_V2_MOVE_A2B_BLOCK_COMMAND … #define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND … #define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND … #define _DMA_V2_INIT_A_COMMAND … #define _DMA_V2_INIT_A_BLOCK_COMMAND … #define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND … #define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND … #define _DMA_V2_INIT_B_COMMAND … #define _DMA_V2_INIT_B_BLOCK_COMMAND … #define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND … #define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND … #define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND … #define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND … #define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND … #define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND … #define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND … #define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND … #define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND … #define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND … #define _DMA_V2_CONFIG_CHANNEL_COMMAND … #define _DMA_V2_SET_CHANNEL_PARAM_COMMAND … #define _DMA_V2_SET_CRUN_COMMAND … /* Channel Parameter IDs */ #define _DMA_V2_PACKING_SETUP_PARAM … #define _DMA_V2_STRIDE_A_PARAM … #define _DMA_V2_ELEM_CROPPING_A_PARAM … #define _DMA_V2_WIDTH_A_PARAM … #define _DMA_V2_STRIDE_B_PARAM … #define _DMA_V2_ELEM_CROPPING_B_PARAM … #define _DMA_V2_WIDTH_B_PARAM … #define _DMA_V2_HEIGHT_PARAM … #define _DMA_V2_QUEUED_CMDS … /* Parameter Constants */ #define _DMA_V2_ZERO_EXTEND … #define _DMA_V2_SIGN_EXTEND … /* SLAVE address map */ #define _DMA_V2_SEL_FSM_CMD … #define _DMA_V2_SEL_CH_REG … #define _DMA_V2_SEL_CONN_GROUP … #define _DMA_V2_SEL_DEV_INTERF … #define _DMA_V2_ADDR_SEL_COMP_IDX … #define _DMA_V2_ADDR_SEL_COMP_BITS … #define _DMA_V2_ADDR_SEL_CH_REG_IDX … #define _DMA_V2_ADDR_SEL_CH_REG_BITS … #define _DMA_V2_ADDR_SEL_PARAM_IDX … #define _DMA_V2_ADDR_SEL_PARAM_BITS … #define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX … #define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS … #define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX … #define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS … #define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX … #define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS … #define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX … #define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS … #define _DMA_V2_FSM_GROUP_CMD_IDX … #define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX … #define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX … #define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX … #define _DMA_V2_FSM_GROUP_FSM_PACK_IDX … #define _DMA_V2_FSM_GROUP_FSM_REQ_IDX … #define _DMA_V2_FSM_GROUP_FSM_WR_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX … #define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX … #define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX … #define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX … #define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX … #define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX … #define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX … #define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX … #define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX … #define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX … #define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX … #define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX … #define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX … #define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX … #define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX … #define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX … #define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX … #define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX … #define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX … #define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX … #define _DMA_V2_DEV_INTERF_MAX_BURST_IDX … #define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN … #endif /* _dma_v2_defs_h */
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