/* SPDX-License-Identifier: GPL-2.0 */ /* * Support for Intel Camera Imaging ISP subsystem. * Copyright (c) 2015, Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ /* Version */ #define RTL_VERSION /* instruction pipeline depth */ #define ISP_BRANCHDELAY … /* bus */ #define ISP_BUS_WIDTH … #define ISP_BUS_ADDR_WIDTH … #define ISP_BUS_BURST_SIZE … /* data-path */ #define ISP_SCALAR_WIDTH … #define ISP_SLICE_NELEMS … #define ISP_VEC_NELEMS … #define ISP_VEC_ELEMBITS … #define ISP_VEC_ELEM8BITS … #define ISP_CLONE_DATAPATH_IS_16 … /* memories */ #define ISP_DMEM_DEPTH … #define ISP_DMEM_BSEL_DOWNSAMPLE … #define ISP_VMEM_DEPTH … #define ISP_VMEM_BSEL_DOWNSAMPLE … #define ISP_VMEM_ELEMBITS … #define ISP_VMEM_ELEM_PRECISION … #define ISP_PMEM_DEPTH … #define ISP_PMEM_WIDTH … #define ISP_VAMEM_ADDRESS_BITS … #define ISP_VAMEM_ELEMBITS … #define ISP_VAMEM_DEPTH … #define ISP_VAMEM_ALIGNMENT … #define ISP_VA_ADDRESS_WIDTH … #define ISP_VEC_VALSU_LATENCY … #define ISP_HIST_ADDRESS_BITS … #define ISP_HIST_ALIGNMENT … #define ISP_HIST_COMP_IN_PREC … #define ISP_HIST_DEPTH … #define ISP_HIST_WIDTH … #define ISP_HIST_COMPONENTS … /* program counter */ #define ISP_PC_WIDTH … /* Template switches */ #define ISP_SHIELD_INPUT_DMEM … #define ISP_SHIELD_OUTPUT_DMEM … #define ISP_SHIELD_INPUT_VMEM … #define ISP_SHIELD_OUTPUT_VMEM … #define ISP_SHIELD_INPUT_PMEM … #define ISP_SHIELD_OUTPUT_PMEM … #define ISP_SHIELD_INPUT_HIST … #define ISP_SHIELD_OUTPUT_HIST … /* When LUT is select the shielding is always on */ #define ISP_SHIELD_INPUT_VAMEM … #define ISP_SHIELD_OUTPUT_VAMEM … #define ISP_HAS_IRQ … #define ISP_HAS_SOFT_RESET … #define ISP_HAS_VEC_DIV … #define ISP_HAS_VFU_W_2O … #define ISP_HAS_DEINT3 … #define ISP_HAS_LUT … #define ISP_HAS_HIST … #define ISP_HAS_VALSU … #define ISP_HAS_3rdVALSU … #define ISP_VRF1_HAS_2P … #define ISP_SRU_GUARDING … #define ISP_VLSU_GUARDING … #define ISP_VRF_RAM … #define ISP_SRF_RAM … #define ISP_SPLIT_VMUL_VADD_IS … #define ISP_RFSPLIT_FPGA … /* RSN or Bus pipelining */ #define ISP_RSN_PIPE … #define ISP_VSF_BUS_PIPE … /* extra slave port to vmem */ #define ISP_IF_VMEM … #define ISP_GDC_VMEM … /* Streaming ports */ #define ISP_IF … #define ISP_IF_B … #define ISP_GDC … #define ISP_SCL … #define ISP_GPFIFO … #define ISP_SP … /* Removing Issue Slot(s) */ #define ISP_HAS_NOT_SIMD_IS2 … #define ISP_HAS_NOT_SIMD_IS3 … #define ISP_HAS_NOT_SIMD_IS4 … #define ISP_HAS_NOT_SIMD_IS4_VADD … #define ISP_HAS_NOT_SIMD_IS5 … #define ISP_HAS_NOT_SIMD_IS6 … #define ISP_HAS_NOT_SIMD_IS7 … #define ISP_HAS_NOT_SIMD_IS8 … /* ICache */ #define ISP_ICACHE … #define ISP_ICACHE_ONLY … #define ISP_ICACHE_PREFETCH … #define ISP_ICACHE_INDEX_BITS … #define ISP_ICACHE_SET_BITS … #define ISP_ICACHE_BLOCKS_PER_SET_BITS … /* Experimental Flags */ #define ISP_EXP_1 … #define ISP_EXP_2 … #define ISP_EXP_3 … #define ISP_EXP_4 … #define ISP_EXP_5 … #define ISP_EXP_6 … /* Derived values */ #define ISP_LOG2_PMEM_WIDTH … #define ISP_VEC_WIDTH … #define ISP_SLICE_WIDTH … #define ISP_VMEM_WIDTH … #define ISP_VMEM_ALIGN … #define ISP_SIMDLSU … #define ISP_LSU_IMM_BITS … /* convenient shortcuts for software*/ #define ISP_NWAY … #define NBITS … #define _isp_ceil_div(a, b) … #define ISP_VEC_ALIGN … /* register file sizes */ #define ISP_RF0_SIZE … #define ISP_RF1_SIZE … #define ISP_RF2_SIZE … #define ISP_RF3_SIZE … #define ISP_RF4_SIZE … #define ISP_RF5_SIZE … #define ISP_RF6_SIZE … #define ISP_RF7_SIZE … #define ISP_RF8_SIZE … #define ISP_RF9_SIZE … #define ISP_RF10_SIZE … #define ISP_RF11_SIZE … #define ISP_SRF1_SIZE … #define ISP_SRF2_SIZE … #define ISP_SRF3_SIZE … #define ISP_SRF4_SIZE … #define ISP_SRF5_SIZE … #define ISP_FRF0_SIZE … #define ISP_FRF1_SIZE … #define ISP_FRF2_SIZE … #define ISP_FRF3_SIZE … #define ISP_FRF4_SIZE … #define ISP_FRF5_SIZE … #define ISP_FRF6_SIZE … /* register file read latency */ #define ISP_VRF1_READ_LAT … #define ISP_VRF2_READ_LAT … #define ISP_VRF3_READ_LAT … #define ISP_VRF4_READ_LAT … #define ISP_VRF5_READ_LAT … #define ISP_VRF6_READ_LAT … #define ISP_VRF7_READ_LAT … #define ISP_VRF8_READ_LAT … #define ISP_SRF1_READ_LAT … #define ISP_SRF2_READ_LAT … #define ISP_SRF3_READ_LAT … #define ISP_SRF4_READ_LAT … #define ISP_SRF5_READ_LAT … #define ISP_SRF5_READ_LAT … /* immediate sizes */ #define ISP_IS1_IMM_BITS … #define ISP_IS2_IMM_BITS … #define ISP_IS3_IMM_BITS … #define ISP_IS4_IMM_BITS … #define ISP_IS5_IMM_BITS … #define ISP_IS6_IMM_BITS … #define ISP_IS7_IMM_BITS … #define ISP_IS8_IMM_BITS … #define ISP_IS9_IMM_BITS … /* fifo depths */ #define ISP_IF_FIFO_DEPTH … #define ISP_IF_B_FIFO_DEPTH … #define ISP_DMA_FIFO_DEPTH … #define ISP_OF_FIFO_DEPTH … #define ISP_GDC_FIFO_DEPTH … #define ISP_SCL_FIFO_DEPTH … #define ISP_GPFIFO_FIFO_DEPTH … #define ISP_SP_FIFO_DEPTH …
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