/* SPDX-License-Identifier: GPL-2.0 */ /* * Support for Intel Camera Imaging ISP subsystem. * Copyright (c) 2015, Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ #ifndef _mipi_backend_defs_h #define _mipi_backend_defs_h #include "mipi_backend_common_defs.h" #define MIPI_BACKEND_REG_ALIGN … #define _HRT_MIPI_BACKEND_NOF_IRQS … // SH Backend Register IDs #define _HRT_MIPI_BACKEND_ENABLE_REG_IDX … #define _HRT_MIPI_BACKEND_STATUS_REG_IDX … //#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_IDX 2 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX … #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG1_IDX … #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG2_IDX … #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG3_IDX … #define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX … #define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX … #define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX … #define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX … #define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_IDX … //// #define _HRT_MIPI_BACKEND_CUST_EN_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P1_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P2_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P3_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P0_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P1_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P2_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P3_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P0_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P1_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P2_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P3_REG_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX … //// #define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX … #define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX … //#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_IDX 28 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX … #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_IDX … #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_IDX … #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_IDX … #define _HRT_MIPI_BACKEND_NOF_REGISTERS … #define _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX … ///////////////////////////////////////////////////////////////////////////////////////////////////// #define _HRT_MIPI_BACKEND_ENABLE_REG_WIDTH … #define _HRT_MIPI_BACKEND_STATUS_REG_WIDTH … //#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_WIDTH 1 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG_WIDTH … #define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_WIDTH … #define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_WIDTH … #define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_WIDTH … #define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_WIDTH … #define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_WIDTH … #define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_WIDTH … #define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_WIDTH … //#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_WIDTH 1 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_WIDTH 7 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_WIDTH 7 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_WIDTH 7 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_WIDTH 7 ///////////////////////////////////////////////////////////////////////////////////////////////////// #define _HRT_MIPI_BACKEND_NOF_SP_LUT_ENTRIES … //#define _HRT_MIPI_BACKEND_MAX_NOF_LP_LUT_ENTRIES 16 // to satisfy hss model static array declaration #define _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH … #define _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH … #define _HRT_MIPI_BACKEND_PACKET_ID_WIDTH … #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB … #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) … #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) … #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) … #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) … #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) … #define _HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) … #define _HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) … #define _HRT_MIPI_BACKEND_STREAMING_WIDTH(pix_width) … /*************************************************************************************************/ /* Custom Decoding */ /* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */ /*************************************************************************************************/ #define _HRT_MIPI_BACKEND_CUST_EN_IDX … #define _HRT_MIPI_BACKEND_CUST_EN_DATAID_IDX … #define _HRT_MIPI_BACKEND_CUST_EN_HIGH_PREC_IDX … #define _HRT_MIPI_BACKEND_CUST_EN_WIDTH … #define _HRT_MIPI_BACKEND_CUST_MODE_ALL … #define _HRT_MIPI_BACKEND_CUST_MODE_ONE … #define _HRT_MIPI_BACKEND_CUST_EN_OPTION_IDX … /* Data State config = {get_bits(6bits), valid(1bit)} */ #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S0_IDX … #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S1_IDX … #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S2_IDX … #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_WIDTH … #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_VALID_IDX … #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_GETBITS_IDX … /* Pixel Extractor config */ #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_DATA_ALIGN_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_ALIGN_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_MASK_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_EN_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_WIDTH … /* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P0_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P1_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P2_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P3_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_WIDTH … #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_VALID_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_EOP_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_VALID_IDX … #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_EOP_IDX … /*************************************************************************************************/ /* MIPI backend output streaming interface definition */ /* These parameters define the fields within the streaming bus. These should also be used by the */ /* subsequent block, ie stream2mmio. */ /*************************************************************************************************/ /* The pipe backend - stream2mmio should be design time configurable in */ /* PixWidth - Number of bits per pixel */ /* PPC - Pixel per Clocks */ /* NumSids - Max number of source Ids (ifc's) and derived from that: */ /* SidWidth - Number of bits required for the sid parameter */ /* In order to keep this configurability, below Macro's have these as a parameter */ /*************************************************************************************************/ #define HRT_MIPI_BACKEND_STREAM_EOP_BIT … #define HRT_MIPI_BACKEND_STREAM_SOP_BIT … #define HRT_MIPI_BACKEND_STREAM_EOF_BIT … #define HRT_MIPI_BACKEND_STREAM_SOF_BIT … #define HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT … #define HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) … #define HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, p) … #define HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) … #define HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, p) … #if 0 //#define HRT_MIPI_BACKEND_STREAM_PIX_BITS 14 //#define HRT_MIPI_BACKEND_STREAM_CHID_BITS 4 //#define HRT_MIPI_BACKEND_STREAM_PPC 4 #endif #define HRT_MIPI_BACKEND_STREAM_BITS(sid_width, ppc, pix_width) … /* SP and LP LUT BIT POSITIONS */ #define HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT … #define HRT_MIPI_BACKEND_LUT_SID_LS_BIT … #define HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) … #define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) … #define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) … #define HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) … #define HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) … /* #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 */ #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) … #define HRT_MIPI_BACKEND_LP_LUT_BITS(sid_width) … // temp solution //#define HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT + 1 // 8 //#define HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT + 1 // 9 //#define HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT + 1 // 10 //#define HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT + 1 // 11 //#define HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT + 1 // 12 //#define HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 25 //#define HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT + 1 // 26 //#define HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 39 //#define HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT + 1 // 40 //#define HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 53 //#define HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT + 1 // 54 //#define HRT_MIPI_BACKEND_STREAM_PIXD_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 67 // vc hidden in pixb data (passed as raw12 the pipe) #define HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) … #define HRT_MIPI_BACKEND_STREAM_VC_MS_BIT(sid_width, ppc, pix_width) … #endif /* _mipi_backend_defs_h */
Codebase Browser
linux