/* SPDX-License-Identifier: GPL-2.0 */ /* * Support for Intel Camera Imaging ISP subsystem. * Copyright (c) 2015, Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ #ifndef HRT_GDC_v2_defs_h_ #define HRT_GDC_v2_defs_h_ #define HRT_GDC_IS_V2 #define HRT_GDC_N … #define HRT_GDC_FRAC_BITS … #define HRT_GDC_BLI_FRAC_BITS … #define HRT_GDC_BLI_COEF_ONE … #define HRT_GDC_BCI_COEF_BITS … #define HRT_GDC_BCI_COEF_ONE … /* The supported range is [-256, .., +256] */ /* in 14-bit signed notation, */ /* We need all ten bits (MSB must be zero). */ /* -s is inserted to solve this issue, and */ /* therefore "1" is equal to +256. */ #define HRT_GDC_BCI_COEF_MASK … #define HRT_GDC_LUT_BYTES … /* 2 bytes per coefficient */ #define _HRT_GDC_REG_ALIGN … // 31 30 29 25 24 0 // |-----|---|--------|------------------------| // | CMD | C | Reg_ID | Value | // There are just two commands possible for the GDC block: // 1 - Configure reg // 0 - Data token // C - Reserved bit // Used in protocol to indicate whether it is C-run or other type of runs // In case of C-run, this bit has a value of 1, for all the other runs, it is 0. // Reg_ID - Address of the register to be configured // Value - Value to store to the addressed register, maximum of 24 bits // Configure reg command is not followed by any other token. // The address of the register and the data to be filled in is contained in the same token // When the first data token is received, it must be: // 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or, // 2. P0'X (device configured in one of the tetragon modes) // After the first data token is received, pre-defined number of tokens with the following meaning follow: // 1. two tokens: SRC address ; DST address // 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address #define HRT_GDC_CONFIG_CMD … #define HRT_GDC_DATA_CMD … #define HRT_GDC_CMD_POS … #define HRT_GDC_CMD_BITS … #define HRT_GDC_CRUN_POS … #define HRT_GDC_REG_ID_POS … #define HRT_GDC_REG_ID_BITS … #define HRT_GDC_DATA_POS … #define HRT_GDC_DATA_BITS … #define HRT_GDC_FRYIPXFRX_BITS … #define HRT_GDC_P0X_BITS … #define HRT_GDC_MAX_OXDIM … #define HRT_GDC_MAX_OYDIM … #define HRT_GDC_MAX_IXDIM … #define HRT_GDC_MAX_IYDIM … #define HRT_GDC_MAX_DS_FAC … #define HRT_GDC_MAX_DX … #define HRT_GDC_MAX_DY … /* GDC lookup tables entries are 10 bits values, but they're stored 2 by 2 as 32 bit values, yielding 16 bits per entry. A GDC lookup table contains 64 * 4 elements */ #define HRT_GDC_PERF_1_1_pix … #define HRT_GDC_PERF_2_1_pix … #define HRT_GDC_PERF_1_2_pix … #define HRT_GDC_PERF_2_2_pix … #define HRT_GDC_NND_MODE … #define HRT_GDC_BLI_MODE … #define HRT_GDC_BCI_MODE … #define HRT_GDC_LUT_MODE … #define HRT_GDC_SCAN_STB … #define HRT_GDC_SCAN_STR … #define HRT_GDC_MODE_SCALING … #define HRT_GDC_MODE_TETRAGON … #define HRT_GDC_LUT_COEFF_OFFSET … #define HRT_GDC_FRY_BIT_OFFSET … // FRYIPXFRX is the only register where we store two values in one field, // to save one token in the scaling protocol. // Like this, we have three tokens in the scaling protocol, // Otherwise, we would have had four. // The register bit-map is: // 31 26 25 16 15 10 9 0 // |------|----------|------|----------| // | XXXX | FRY | IPX | FRX | #define HRT_GDC_CE_FSM0_POS … #define HRT_GDC_CE_FSM0_LEN … #define HRT_GDC_CE_OPY_POS … #define HRT_GDC_CE_OPY_LEN … #define HRT_GDC_CE_OPX_POS … #define HRT_GDC_CE_OPX_LEN … // CHK_ENGINE register bit-map: // 31 16 15 2 1 0 // |----------------|-----------|----| // | OPX | OPY |FSM0| // However, for the time being at least, // this implementation is meaningless in hss model, // So, we just return 0 #define HRT_GDC_CHK_ENGINE_IDX … #define HRT_GDC_WOIX_IDX … #define HRT_GDC_WOIY_IDX … #define HRT_GDC_BPP_IDX … #define HRT_GDC_FRYIPXFRX_IDX … #define HRT_GDC_OXDIM_IDX … #define HRT_GDC_OYDIM_IDX … #define HRT_GDC_SRC_ADDR_IDX … #define HRT_GDC_SRC_END_ADDR_IDX … #define HRT_GDC_SRC_WRAP_ADDR_IDX … #define HRT_GDC_SRC_STRIDE_IDX … #define HRT_GDC_DST_ADDR_IDX … #define HRT_GDC_DST_STRIDE_IDX … #define HRT_GDC_DX_IDX … #define HRT_GDC_DY_IDX … #define HRT_GDC_P0X_IDX … #define HRT_GDC_P0Y_IDX … #define HRT_GDC_P1X_IDX … #define HRT_GDC_P1Y_IDX … #define HRT_GDC_P2X_IDX … #define HRT_GDC_P2Y_IDX … #define HRT_GDC_P3X_IDX … #define HRT_GDC_P3Y_IDX … #define HRT_GDC_PERF_POINT_IDX … #define HRT_GDC_INTERP_TYPE_IDX … #define HRT_GDC_SCAN_IDX … #define HRT_GDC_PROC_MODE_IDX … #define HRT_GDC_LUT_IDX … #endif /* HRT_GDC_v2_defs_h_ */
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