/* SPDX-License-Identifier: GPL-2.0 */ /* * Support for Intel Camera Imaging ISP subsystem. * Copyright (c) 2015, Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ #ifndef _input_system_ctrl_defs_h #define _input_system_ctrl_defs_h #define _INPUT_SYSTEM_CTRL_REG_ALIGN … /* --------------------------------------------------*/ /* --------------------------------------------------*/ /* REGISTER INFO */ /* --------------------------------------------------*/ // Number of registers #define ISYS_CTRL_NOF_REGS … // Register id's of MMIO slave accessible registers #define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID … #define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID … #define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID … #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID … #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID … #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID … #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID … #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID … #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID … #define ISYS_CTRL_ACQ_START_ADDR_REG_ID … #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID … #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID … #define ISYS_CTRL_INIT_REG_ID … #define ISYS_CTRL_LAST_COMMAND_REG_ID … #define ISYS_CTRL_NEXT_COMMAND_REG_ID … #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID … #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID … #define ISYS_CTRL_FSM_STATE_INFO_REG_ID … #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID … #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID … #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID … #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID … #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID … /* register reset value */ #define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL … #define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL … #define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL … #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL … #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL … #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL … #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL … #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL … #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL … #define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL … #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL … #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL … #define ISYS_CTRL_INIT_REG_RSTVAL … #define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL … #define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL … #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL … #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL … #define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL … #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL … #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL … #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL … #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL … #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL … /* register width value */ #define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH … #define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH … #define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH … #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH … #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH … #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH … #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH … #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH … #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH … #define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH … #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH … #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH … #define ISYS_CTRL_INIT_REG_WIDTH … #define ISYS_CTRL_LAST_COMMAND_REG_WIDTH … #define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH … #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH … #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH … #define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH … #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH … #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH … #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH … #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH … #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH … /* bit definitions */ /* --------------------------------------------------*/ /* TOKEN INFO */ /* --------------------------------------------------*/ /* InpSysCaptFramesAcq 1/0 [3:0] - 'b0000 [7:4] - CaptPortId, CaptA-'b0000 CaptB-'b0001 CaptC-'b0010 [31:16] - NOF_frames InpSysCaptFrameExt 2/0 [3:0] - 'b0001' [7:4] - CaptPortId, 'b0000 - CaptA 'b0001 - CaptB 'b0010 - CaptC 2/1 [31:0] - external capture address InpSysAcqFrame 2/0 [3:0] - 'b0010, [31:4] - NOF_ext_mem_words 2/1 [31:0] - external memory read start address InpSysOverruleON 1/0 [3:0] - 'b0011, [7:4] - overrule port id (opid) 'b0000 - CaptA 'b0001 - CaptB 'b0010 - CaptC 'b0011 - Acq 'b0100 - DMA InpSysOverruleOFF 1/0 [3:0] - 'b0100, [7:4] - overrule port id (opid) 'b0000 - CaptA 'b0001 - CaptB 'b0010 - CaptC 'b0011 - Acq 'b0100 - DMA InpSysOverruleCmd 2/0 [3:0] - 'b0101, [7:4] - overrule port id (opid) 'b0000 - CaptA 'b0001 - CaptB 'b0010 - CaptC 'b0011 - Acq 'b0100 - DMA 2/1 [31:0] - command token value for port opid acknowledge tokens: InpSysAckCFA 1/0 [3:0] - 'b0000 [7:4] - CaptPortId, CaptA-'b0000 CaptB- 'b0001 CaptC-'b0010 [31:16] - NOF_frames InpSysAckCFE 1/0 [3:0] - 'b0001' [7:4] - CaptPortId, 'b0000 - CaptA 'b0001 - CaptB 'b0010 - CaptC InpSysAckAF 1/0 [3:0] - 'b0010 InpSysAckOverruleON 1/0 [3:0] - 'b0011, [7:4] - overrule port id (opid) 'b0000 - CaptA 'b0001 - CaptB 'b0010 - CaptC 'b0011 - Acq 'b0100 - DMA InpSysAckOverruleOFF 1/0 [3:0] - 'b0100, [7:4] - overrule port id (opid) 'b0000 - CaptA 'b0001 - CaptB 'b0010 - CaptC 'b0011 - Acq 'b0100 - DMA InpSysAckOverrule 2/0 [3:0] - 'b0101, [7:4] - overrule port id (opid) 'b0000 - CaptA 'b0001 - CaptB 'b0010 - CaptC 'b0011 - Acq 'b0100 - DMA 2/1 [31:0] - acknowledge token value from port opid */ /* Command and acknowledge tokens IDs */ #define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID … #define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID … #define ISYS_CTRL_ACQ_FRAME_TOKEN_ID … #define ISYS_CTRL_OVERRULE_ON_TOKEN_ID … #define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID … #define ISYS_CTRL_OVERRULE_TOKEN_ID … #define ISYS_CTRL_ACK_CFA_TOKEN_ID … #define ISYS_CTRL_ACK_CFE_TOKEN_ID … #define ISYS_CTRL_ACK_AF_TOKEN_ID … #define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID … #define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID … #define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID … #define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID … #define ISYS_CTRL_TOKEN_ID_MSB … #define ISYS_CTRL_TOKEN_ID_LSB … #define ISYS_CTRL_PORT_ID_TOKEN_MSB … #define ISYS_CTRL_PORT_ID_TOKEN_LSB … #define ISYS_CTRL_NOF_CAPT_TOKEN_MSB … #define ISYS_CTRL_NOF_CAPT_TOKEN_LSB … #define ISYS_CTRL_NOF_EXT_TOKEN_MSB … #define ISYS_CTRL_NOF_EXT_TOKEN_LSB … #define ISYS_CTRL_TOKEN_ID_IDX … #define ISYS_CTRL_TOKEN_ID_BITS … #define ISYS_CTRL_PORT_ID_IDX … #define ISYS_CTRL_PORT_ID_BITS … #define ISYS_CTRL_NOF_CAPT_IDX … #define ISYS_CTRL_NOF_CAPT_BITS … #define ISYS_CTRL_NOF_EXT_IDX … #define ISYS_CTRL_NOF_EXT_BITS … #define ISYS_CTRL_PORT_ID_CAPT_A … #define ISYS_CTRL_PORT_ID_CAPT_B … #define ISYS_CTRL_PORT_ID_CAPT_C … #define ISYS_CTRL_PORT_ID_ACQUISITION … #define ISYS_CTRL_PORT_ID_DMA_CAPT_A … #define ISYS_CTRL_PORT_ID_DMA_CAPT_B … #define ISYS_CTRL_PORT_ID_DMA_CAPT_C … #define ISYS_CTRL_PORT_ID_DMA_ACQ … #define ISYS_CTRL_NO_ACQ_ACK … #define ISYS_CTRL_NO_DMA_ACK … #define ISYS_CTRL_NO_CAPT_ACK … #endif /* _input_system_ctrl_defs_h */
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