/* SPDX-License-Identifier: GPL-2.0 */ /* * Support for Intel Camera Imaging ISP subsystem. * Copyright (c) 2010-2015, Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ #ifndef __INPUT_SYSTEM_2400_LOCAL_H_INCLUDED__ #define __INPUT_SYSTEM_2400_LOCAL_H_INCLUDED__ #include "input_system_defs.h" /* HIVE_ISYS_GPREG_MULTICAST_A_IDX,... */ /* * _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX, * _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX,... */ #include "css_receiver_2400_defs.h" #include "isp_capture_defs.h" #include "isp_acquisition_defs.h" #include "input_system_ctrl_defs.h" struct target_cfg2400_s { … }; // Configuration of a channel. struct channel_cfg_s { … }; // Complete configuration for input system. struct input_system_cfg2400_s { … }; /* * For each MIPI port */ #define _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX … #define _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX … #define _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX … #define _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX … #define _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX … /* new regs for each MIPI port w.r.t. 2300 */ #define _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX … #define _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX … #define _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX … /* _HRT_CSS_RECEIVER_2400_COMP_FORMAT_REG_IDX is not defined per MIPI port but per channel */ /* _HRT_CSS_RECEIVER_2400_COMP_PREDICT_REG_IDX is not defined per MIPI port but per channel */ #define _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX … #define _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX … #define _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX … #define _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX … #define _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX … #define _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX … #define _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX … #define _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX … #define _HRT_CSS_RECEIVER_RAW18_REG_IDX … #define _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX … #define _HRT_CSS_RECEIVER_RAW16_REG_IDX … /* Previously MIPI port regs, now 2x2 logical channel regs */ #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG0_IDX … #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG1_IDX … #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG0_IDX … #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG1_IDX … #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG0_IDX … #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG1_IDX … #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG0_IDX … #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG1_IDX … /* Second backend is at offset 0x0700 w.r.t. the first port at offset 0x0100 */ #define _HRT_CSS_BE_OFFSET … #define _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX … #define _HRT_CSS_RECEIVER_BE_SRST_REG_IDX … #define _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX … #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX … #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX … #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX … #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX … #define _HRT_CSS_RECEIVER_BE_SEL_REG_IDX … #define _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX … #define _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX … #define _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX … #define _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX … #define _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX … #define _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT … #define _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT … #define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT … #define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT … #define _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT … #define _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT … #define _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX … #define _HRT_CSS_RECEIVER_DATA_TIMEOUT_IDX … #define _HRT_CSS_RECEIVER_DATA_TIMEOUT_BITS … mipi_format_2400_t; #define N_MIPI_FORMAT_CUSTOM … /* The number of stores for compressed format types */ #define N_MIPI_COMPRESSOR_CONTEXT … rx_irq_info_t; /* NOTE: The base has already an offset of 0x0100 */ static const hrt_address __maybe_unused MIPI_PORT_OFFSET[N_MIPI_PORT_ID] = …; static const hrt_address __maybe_unused SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = …; #endif /* __INPUT_SYSTEM_LOCAL_H_INCLUDED__ */
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