/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2018 MediaTek Inc. * Author: Weiyi Lu <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT8183_H #define _DT_BINDINGS_CLK_MT8183_H /* APMIXED */ #define CLK_APMIXED_ARMPLL_LL … #define CLK_APMIXED_ARMPLL_L … #define CLK_APMIXED_CCIPLL … #define CLK_APMIXED_MAINPLL … #define CLK_APMIXED_UNIV2PLL … #define CLK_APMIXED_MSDCPLL … #define CLK_APMIXED_MMPLL … #define CLK_APMIXED_MFGPLL … #define CLK_APMIXED_TVDPLL … #define CLK_APMIXED_APLL1 … #define CLK_APMIXED_APLL2 … #define CLK_APMIXED_SSUSB_26M … #define CLK_APMIXED_APPLL_26M … #define CLK_APMIXED_MIPIC0_26M … #define CLK_APMIXED_MDPLLGP_26M … #define CLK_APMIXED_MMSYS_26M … #define CLK_APMIXED_UFS_26M … #define CLK_APMIXED_MIPIC1_26M … #define CLK_APMIXED_MEMPLL_26M … #define CLK_APMIXED_CLKSQ_LVPLL_26M … #define CLK_APMIXED_MIPID0_26M … #define CLK_APMIXED_MIPID1_26M … #define CLK_APMIXED_NR_CLK … /* TOPCKGEN */ #define CLK_TOP_MUX_AXI … #define CLK_TOP_MUX_MM … #define CLK_TOP_MUX_CAM … #define CLK_TOP_MUX_MFG … #define CLK_TOP_MUX_CAMTG … #define CLK_TOP_MUX_UART … #define CLK_TOP_MUX_SPI … #define CLK_TOP_MUX_MSDC50_0_HCLK … #define CLK_TOP_MUX_MSDC50_0 … #define CLK_TOP_MUX_MSDC30_1 … #define CLK_TOP_MUX_MSDC30_2 … #define CLK_TOP_MUX_AUDIO … #define CLK_TOP_MUX_AUD_INTBUS … #define CLK_TOP_MUX_FPWRAP_ULPOSC … #define CLK_TOP_MUX_SCP … #define CLK_TOP_MUX_ATB … #define CLK_TOP_MUX_SSPM … #define CLK_TOP_MUX_DPI0 … #define CLK_TOP_MUX_SCAM … #define CLK_TOP_MUX_AUD_1 … #define CLK_TOP_MUX_AUD_2 … #define CLK_TOP_MUX_DISP_PWM … #define CLK_TOP_MUX_SSUSB_TOP_XHCI … #define CLK_TOP_MUX_USB_TOP … #define CLK_TOP_MUX_SPM … #define CLK_TOP_MUX_I2C … #define CLK_TOP_MUX_F52M_MFG … #define CLK_TOP_MUX_SENINF … #define CLK_TOP_MUX_DXCC … #define CLK_TOP_MUX_CAMTG2 … #define CLK_TOP_MUX_AUD_ENG1 … #define CLK_TOP_MUX_AUD_ENG2 … #define CLK_TOP_MUX_FAES_UFSFDE … #define CLK_TOP_MUX_FUFS … #define CLK_TOP_MUX_IMG … #define CLK_TOP_MUX_DSP … #define CLK_TOP_MUX_DSP1 … #define CLK_TOP_MUX_DSP2 … #define CLK_TOP_MUX_IPU_IF … #define CLK_TOP_MUX_CAMTG3 … #define CLK_TOP_MUX_CAMTG4 … #define CLK_TOP_MUX_PMICSPI … #define CLK_TOP_SYSPLL_CK … #define CLK_TOP_SYSPLL_D2 … #define CLK_TOP_SYSPLL_D3 … #define CLK_TOP_SYSPLL_D5 … #define CLK_TOP_SYSPLL_D7 … #define CLK_TOP_SYSPLL_D2_D2 … #define CLK_TOP_SYSPLL_D2_D4 … #define CLK_TOP_SYSPLL_D2_D8 … #define CLK_TOP_SYSPLL_D2_D16 … #define CLK_TOP_SYSPLL_D3_D2 … #define CLK_TOP_SYSPLL_D3_D4 … #define CLK_TOP_SYSPLL_D3_D8 … #define CLK_TOP_SYSPLL_D5_D2 … #define CLK_TOP_SYSPLL_D5_D4 … #define CLK_TOP_SYSPLL_D7_D2 … #define CLK_TOP_SYSPLL_D7_D4 … #define CLK_TOP_UNIVPLL_CK … #define CLK_TOP_UNIVPLL_D2 … #define CLK_TOP_UNIVPLL_D3 … #define CLK_TOP_UNIVPLL_D5 … #define CLK_TOP_UNIVPLL_D7 … #define CLK_TOP_UNIVPLL_D2_D2 … #define CLK_TOP_UNIVPLL_D2_D4 … #define CLK_TOP_UNIVPLL_D2_D8 … #define CLK_TOP_UNIVPLL_D3_D2 … #define CLK_TOP_UNIVPLL_D3_D4 … #define CLK_TOP_UNIVPLL_D3_D8 … #define CLK_TOP_UNIVPLL_D5_D2 … #define CLK_TOP_UNIVPLL_D5_D4 … #define CLK_TOP_UNIVPLL_D5_D8 … #define CLK_TOP_APLL1_CK … #define CLK_TOP_APLL1_D2 … #define CLK_TOP_APLL1_D4 … #define CLK_TOP_APLL1_D8 … #define CLK_TOP_APLL2_CK … #define CLK_TOP_APLL2_D2 … #define CLK_TOP_APLL2_D4 … #define CLK_TOP_APLL2_D8 … #define CLK_TOP_TVDPLL_CK … #define CLK_TOP_TVDPLL_D2 … #define CLK_TOP_TVDPLL_D4 … #define CLK_TOP_TVDPLL_D8 … #define CLK_TOP_TVDPLL_D16 … #define CLK_TOP_MSDCPLL_CK … #define CLK_TOP_MSDCPLL_D2 … #define CLK_TOP_MSDCPLL_D4 … #define CLK_TOP_MSDCPLL_D8 … #define CLK_TOP_MSDCPLL_D16 … #define CLK_TOP_AD_OSC_CK … #define CLK_TOP_OSC_D2 … #define CLK_TOP_OSC_D4 … #define CLK_TOP_OSC_D8 … #define CLK_TOP_OSC_D16 … #define CLK_TOP_F26M_CK_D2 … #define CLK_TOP_MFGPLL_CK … #define CLK_TOP_UNIVP_192M_CK … #define CLK_TOP_UNIVP_192M_D2 … #define CLK_TOP_UNIVP_192M_D4 … #define CLK_TOP_UNIVP_192M_D8 … #define CLK_TOP_UNIVP_192M_D16 … #define CLK_TOP_UNIVP_192M_D32 … #define CLK_TOP_MMPLL_CK … #define CLK_TOP_MMPLL_D4 … #define CLK_TOP_MMPLL_D4_D2 … #define CLK_TOP_MMPLL_D4_D4 … #define CLK_TOP_MMPLL_D5 … #define CLK_TOP_MMPLL_D5_D2 … #define CLK_TOP_MMPLL_D5_D4 … #define CLK_TOP_MMPLL_D6 … #define CLK_TOP_MMPLL_D7 … #define CLK_TOP_CLK26M … #define CLK_TOP_CLK13M … #define CLK_TOP_ULPOSC … #define CLK_TOP_UNIVP_192M … #define CLK_TOP_MUX_APLL_I2S0 … #define CLK_TOP_MUX_APLL_I2S1 … #define CLK_TOP_MUX_APLL_I2S2 … #define CLK_TOP_MUX_APLL_I2S3 … #define CLK_TOP_MUX_APLL_I2S4 … #define CLK_TOP_MUX_APLL_I2S5 … #define CLK_TOP_APLL12_DIV0 … #define CLK_TOP_APLL12_DIV1 … #define CLK_TOP_APLL12_DIV2 … #define CLK_TOP_APLL12_DIV3 … #define CLK_TOP_APLL12_DIV4 … #define CLK_TOP_APLL12_DIVB … #define CLK_TOP_UNIVPLL … #define CLK_TOP_ARMPLL_DIV_PLL1 … #define CLK_TOP_ARMPLL_DIV_PLL2 … #define CLK_TOP_UNIVPLL_D3_D16 … #define CLK_TOP_NR_CLK … /* CAMSYS */ #define CLK_CAM_LARB6 … #define CLK_CAM_DFP_VAD … #define CLK_CAM_CAM … #define CLK_CAM_CAMTG … #define CLK_CAM_SENINF … #define CLK_CAM_CAMSV0 … #define CLK_CAM_CAMSV1 … #define CLK_CAM_CAMSV2 … #define CLK_CAM_CCU … #define CLK_CAM_LARB3 … #define CLK_CAM_NR_CLK … /* INFRACFG_AO */ #define CLK_INFRA_PMIC_TMR … #define CLK_INFRA_PMIC_AP … #define CLK_INFRA_PMIC_MD … #define CLK_INFRA_PMIC_CONN … #define CLK_INFRA_SCPSYS … #define CLK_INFRA_SEJ … #define CLK_INFRA_APXGPT … #define CLK_INFRA_ICUSB … #define CLK_INFRA_GCE … #define CLK_INFRA_THERM … #define CLK_INFRA_I2C0 … #define CLK_INFRA_I2C1 … #define CLK_INFRA_I2C2 … #define CLK_INFRA_I2C3 … #define CLK_INFRA_PWM_HCLK … #define CLK_INFRA_PWM1 … #define CLK_INFRA_PWM2 … #define CLK_INFRA_PWM3 … #define CLK_INFRA_PWM4 … #define CLK_INFRA_PWM … #define CLK_INFRA_UART0 … #define CLK_INFRA_UART1 … #define CLK_INFRA_UART2 … #define CLK_INFRA_UART3 … #define CLK_INFRA_GCE_26M … #define CLK_INFRA_CQ_DMA_FPC … #define CLK_INFRA_BTIF … #define CLK_INFRA_SPI0 … #define CLK_INFRA_MSDC0 … #define CLK_INFRA_MSDC1 … #define CLK_INFRA_MSDC2 … #define CLK_INFRA_MSDC0_SCK … #define CLK_INFRA_DVFSRC … #define CLK_INFRA_GCPU … #define CLK_INFRA_TRNG … #define CLK_INFRA_AUXADC … #define CLK_INFRA_CPUM … #define CLK_INFRA_CCIF1_AP … #define CLK_INFRA_CCIF1_MD … #define CLK_INFRA_AUXADC_MD … #define CLK_INFRA_MSDC1_SCK … #define CLK_INFRA_MSDC2_SCK … #define CLK_INFRA_AP_DMA … #define CLK_INFRA_XIU … #define CLK_INFRA_DEVICE_APC … #define CLK_INFRA_CCIF_AP … #define CLK_INFRA_DEBUGSYS … #define CLK_INFRA_AUDIO … #define CLK_INFRA_CCIF_MD … #define CLK_INFRA_DXCC_SEC_CORE … #define CLK_INFRA_DXCC_AO … #define CLK_INFRA_DRAMC_F26M … #define CLK_INFRA_IRTX … #define CLK_INFRA_DISP_PWM … #define CLK_INFRA_CLDMA_BCLK … #define CLK_INFRA_AUDIO_26M_BCLK … #define CLK_INFRA_SPI1 … #define CLK_INFRA_I2C4 … #define CLK_INFRA_MODEM_TEMP_SHARE … #define CLK_INFRA_SPI2 … #define CLK_INFRA_SPI3 … #define CLK_INFRA_UNIPRO_SCK … #define CLK_INFRA_UNIPRO_TICK … #define CLK_INFRA_UFS_MP_SAP_BCLK … #define CLK_INFRA_MD32_BCLK … #define CLK_INFRA_SSPM … #define CLK_INFRA_UNIPRO_MBIST … #define CLK_INFRA_SSPM_BUS_HCLK … #define CLK_INFRA_I2C5 … #define CLK_INFRA_I2C5_ARBITER … #define CLK_INFRA_I2C5_IMM … #define CLK_INFRA_I2C1_ARBITER … #define CLK_INFRA_I2C1_IMM … #define CLK_INFRA_I2C2_ARBITER … #define CLK_INFRA_I2C2_IMM … #define CLK_INFRA_SPI4 … #define CLK_INFRA_SPI5 … #define CLK_INFRA_CQ_DMA … #define CLK_INFRA_UFS … #define CLK_INFRA_AES_UFSFDE … #define CLK_INFRA_UFS_TICK … #define CLK_INFRA_MSDC0_SELF … #define CLK_INFRA_MSDC1_SELF … #define CLK_INFRA_MSDC2_SELF … #define CLK_INFRA_SSPM_26M_SELF … #define CLK_INFRA_SSPM_32K_SELF … #define CLK_INFRA_UFS_AXI … #define CLK_INFRA_I2C6 … #define CLK_INFRA_AP_MSDC0 … #define CLK_INFRA_MD_MSDC0 … #define CLK_INFRA_USB … #define CLK_INFRA_DEVMPU_BCLK … #define CLK_INFRA_CCIF2_AP … #define CLK_INFRA_CCIF2_MD … #define CLK_INFRA_CCIF3_AP … #define CLK_INFRA_CCIF3_MD … #define CLK_INFRA_SEJ_F13M … #define CLK_INFRA_AES_BCLK … #define CLK_INFRA_I2C7 … #define CLK_INFRA_I2C8 … #define CLK_INFRA_FBIST2FPC … #define CLK_INFRA_NR_CLK … /* PERICFG */ #define CLK_PERI_AXI … #define CLK_PERI_NR_CLK … /* MFGCFG */ #define CLK_MFG_BG3D … #define CLK_MFG_NR_CLK … /* IMG */ #define CLK_IMG_OWE … #define CLK_IMG_WPE_B … #define CLK_IMG_WPE_A … #define CLK_IMG_MFB … #define CLK_IMG_RSC … #define CLK_IMG_DPE … #define CLK_IMG_FDVT … #define CLK_IMG_DIP … #define CLK_IMG_LARB2 … #define CLK_IMG_LARB5 … #define CLK_IMG_NR_CLK … /* MMSYS_CONFIG */ #define CLK_MM_SMI_COMMON … #define CLK_MM_SMI_LARB0 … #define CLK_MM_SMI_LARB1 … #define CLK_MM_GALS_COMM0 … #define CLK_MM_GALS_COMM1 … #define CLK_MM_GALS_CCU2MM … #define CLK_MM_GALS_IPU12MM … #define CLK_MM_GALS_IMG2MM … #define CLK_MM_GALS_CAM2MM … #define CLK_MM_GALS_IPU2MM … #define CLK_MM_MDP_DL_TXCK … #define CLK_MM_IPU_DL_TXCK … #define CLK_MM_MDP_RDMA0 … #define CLK_MM_MDP_RDMA1 … #define CLK_MM_MDP_RSZ0 … #define CLK_MM_MDP_RSZ1 … #define CLK_MM_MDP_TDSHP … #define CLK_MM_MDP_WROT0 … #define CLK_MM_FAKE_ENG … #define CLK_MM_DISP_OVL0 … #define CLK_MM_DISP_OVL0_2L … #define CLK_MM_DISP_OVL1_2L … #define CLK_MM_DISP_RDMA0 … #define CLK_MM_DISP_RDMA1 … #define CLK_MM_DISP_WDMA0 … #define CLK_MM_DISP_COLOR0 … #define CLK_MM_DISP_CCORR0 … #define CLK_MM_DISP_AAL0 … #define CLK_MM_DISP_GAMMA0 … #define CLK_MM_DISP_DITHER0 … #define CLK_MM_DISP_SPLIT … #define CLK_MM_DSI0_MM … #define CLK_MM_DSI0_IF … #define CLK_MM_DPI_MM … #define CLK_MM_DPI_IF … #define CLK_MM_FAKE_ENG2 … #define CLK_MM_MDP_DL_RX … #define CLK_MM_IPU_DL_RX … #define CLK_MM_26M … #define CLK_MM_MMSYS_R2Y … #define CLK_MM_DISP_RSZ … #define CLK_MM_MDP_WDMA0 … #define CLK_MM_MDP_AAL … #define CLK_MM_MDP_CCORR … #define CLK_MM_DBI_MM … #define CLK_MM_DBI_IF … #define CLK_MM_NR_CLK … /* VDEC_GCON */ #define CLK_VDEC_VDEC … #define CLK_VDEC_LARB1 … #define CLK_VDEC_NR_CLK … /* VENC_GCON */ #define CLK_VENC_LARB … #define CLK_VENC_VENC … #define CLK_VENC_JPGENC … #define CLK_VENC_NR_CLK … /* AUDIO */ #define CLK_AUDIO_TML … #define CLK_AUDIO_DAC_PREDIS … #define CLK_AUDIO_DAC … #define CLK_AUDIO_ADC … #define CLK_AUDIO_APLL_TUNER … #define CLK_AUDIO_APLL2_TUNER … #define CLK_AUDIO_24M … #define CLK_AUDIO_22M … #define CLK_AUDIO_AFE … #define CLK_AUDIO_I2S4 … #define CLK_AUDIO_I2S3 … #define CLK_AUDIO_I2S2 … #define CLK_AUDIO_I2S1 … #define CLK_AUDIO_PDN_ADDA6_ADC … #define CLK_AUDIO_TDM … #define CLK_AUDIO_NR_CLK … /* IPU_CONN */ #define CLK_IPU_CONN_IPU … #define CLK_IPU_CONN_AHB … #define CLK_IPU_CONN_AXI … #define CLK_IPU_CONN_ISP … #define CLK_IPU_CONN_CAM_ADL … #define CLK_IPU_CONN_IMG_ADL … #define CLK_IPU_CONN_DAP_RX … #define CLK_IPU_CONN_APB2AXI … #define CLK_IPU_CONN_APB2AHB … #define CLK_IPU_CONN_IPU_CAB1TO2 … #define CLK_IPU_CONN_IPU1_CAB1TO2 … #define CLK_IPU_CONN_IPU2_CAB1TO2 … #define CLK_IPU_CONN_CAB3TO3 … #define CLK_IPU_CONN_CAB2TO1 … #define CLK_IPU_CONN_CAB3TO1_SLICE … #define CLK_IPU_CONN_NR_CLK … /* IPU_ADL */ #define CLK_IPU_ADL_CABGEN … #define CLK_IPU_ADL_NR_CLK … /* IPU_CORE0 */ #define CLK_IPU_CORE0_JTAG … #define CLK_IPU_CORE0_AXI … #define CLK_IPU_CORE0_IPU … #define CLK_IPU_CORE0_NR_CLK … /* IPU_CORE1 */ #define CLK_IPU_CORE1_JTAG … #define CLK_IPU_CORE1_AXI … #define CLK_IPU_CORE1_IPU … #define CLK_IPU_CORE1_NR_CLK … /* MCUCFG */ #define CLK_MCU_MP0_SEL … #define CLK_MCU_MP2_SEL … #define CLK_MCU_BUS_SEL … #define CLK_MCU_NR_CLK … #endif /* _DT_BINDINGS_CLK_MT8183_H */
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