linux/drivers/clk/mediatek/clk-mt8183-apmixedsys.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018 MediaTek Inc.
 *               Weiyi Lu <[email protected]>
 * Copyright (c) 2023 Collabora, Ltd.
 *               AngeloGioacchino Del Regno <[email protected]>
 */

#include <dt-bindings/clock/mt8183-clk.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>

#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"

static const struct mtk_gate_regs apmixed_cg_regs = …;

#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) …

#define GATE_APMIXED(_id, _name, _parent, _shift) …

/*
 * CRITICAL CLOCK:
 * apmixed_appll26m is the toppest clock gate of all PLLs.
 */
static const struct mtk_gate apmixed_clks[] = …;

#define MT8183_PLL_FMAX …
#define MT8183_PLL_FMIN …

#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,		\
			_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg,	\
			_pd_shift, _tuner_reg,  _tuner_en_reg,		\
			_tuner_en_bit, _pcw_reg, _pcw_shift,		\
			_pcw_chg_reg, _div_table) …

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,		\
			_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg,	\
			_pd_shift, _tuner_reg, _tuner_en_reg,		\
			_tuner_en_bit, _pcw_reg, _pcw_shift,		\
			_pcw_chg_reg) …

static const struct mtk_pll_div_table armpll_div_table[] = …;

static const struct mtk_pll_div_table mfgpll_div_table[] = …;

static const struct mtk_pll_data plls[] = …;

static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
{ … }

static const struct of_device_id of_match_clk_mt8183_apmixed[] = …;
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_apmixed);

static struct platform_driver clk_mt8183_apmixed_drv = …;
builtin_platform_driver(…) …

MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;