/* SPDX-License-Identifier: GPL-2.0 */ /* * Support for Intel Camera Imaging ISP subsystem. * Copyright (c) 2015, Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ #ifndef __IA_CSS_EED1_8_PARAM_H #define __IA_CSS_EED1_8_PARAM_H #include "type_support.h" #include "vmem.h" /* needed for VMEM_ARRAY */ #include "ia_css_eed1_8_types.h" /* IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS */ /* Configuration parameters: */ /* Enable median for false color correction * 0: Do not use median * 1: Use median * Default: 1 */ #define EED1_8_FC_ENABLE_MEDIAN … /* Coring Threshold minima * Used in Tint color suppression. * Default: 1 */ #define EED1_8_CORINGTHMIN … /* Define size of the state..... TODO: check if this is the correct place */ /* 4 planes : GR, R, B, GB */ #define NUM_PLANES … /* 5 lines state per color plane input_line_state */ #define EED1_8_STATE_INPUT_BUFFER_HEIGHT … /* Each plane has width equal to half frame line */ #define EED1_8_STATE_INPUT_BUFFER_WIDTH … /* 1 line state per color plane LD_H state */ #define EED1_8_STATE_LD_H_HEIGHT … #define EED1_8_STATE_LD_H_WIDTH … /* 1 line state per color plane LD_V state */ #define EED1_8_STATE_LD_V_HEIGHT … #define EED1_8_STATE_LD_V_WIDTH … /* 1 line (single plane) state for D_Hr state */ #define EED1_8_STATE_D_HR_HEIGHT … #define EED1_8_STATE_D_HR_WIDTH … /* 1 line (single plane) state for D_Hb state */ #define EED1_8_STATE_D_HB_HEIGHT … #define EED1_8_STATE_D_HB_WIDTH … /* 2 lines (single plane) state for D_Vr state */ #define EED1_8_STATE_D_VR_HEIGHT … #define EED1_8_STATE_D_VR_WIDTH … /* 2 line (single plane) state for D_Vb state */ #define EED1_8_STATE_D_VB_HEIGHT … #define EED1_8_STATE_D_VB_WIDTH … /* 2 lines state for R and B (= 2 planes) rb_zipped_state */ #define EED1_8_STATE_RB_ZIPPED_HEIGHT … #define EED1_8_STATE_RB_ZIPPED_WIDTH … #if EED1_8_FC_ENABLE_MEDIAN /* 1 full input line (GR-R color line) for Yc state */ #define EED1_8_STATE_YC_HEIGHT … #define EED1_8_STATE_YC_WIDTH … /* 1 line state per color plane Cg_state */ #define EED1_8_STATE_CG_HEIGHT … #define EED1_8_STATE_CG_WIDTH … /* 1 line state per color plane Co_state */ #define EED1_8_STATE_CO_HEIGHT … #define EED1_8_STATE_CO_WIDTH … /* 1 full input line (GR-R color line) for AbsK state */ #define EED1_8_STATE_ABSK_HEIGHT … #define EED1_8_STATE_ABSK_WIDTH … #endif struct eed1_8_vmem_params { … }; /* EED (Edge Enhancing Demosaic) ISP parameters */ struct eed1_8_dmem_params { … }; #endif /* __IA_CSS_EED1_8_PARAM_H */
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