// SPDX-License-Identifier: GPL-2.0 // // Copyright (c) 2018 MediaTek Inc. // Author: Weiyi Lu <[email protected]> #include <linux/delay.h> #include <linux/mfd/syscon.h> #include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/slab.h> #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" #include <dt-bindings/clock/mt8183-clk.h> static DEFINE_SPINLOCK(mt8183_clk_lock); static const struct mtk_fixed_clk top_fixed_clks[] = …; /* * To retain compatibility with older devicetrees, we keep CLK_TOP_CLK13M * valid, but renamed from "clk13m" (defined as fixed clock in the new * devicetrees) to "clk26m_d2", satisfying the older clock assignments. * This means that on new devicetrees "clk26m_d2" is unused. */ static const struct mtk_fixed_factor top_divs[] = …; static const char * const axi_parents[] = …; static const char * const mm_parents[] = …; static const char * const img_parents[] = …; static const char * const cam_parents[] = …; static const char * const dsp_parents[] = …; static const char * const dsp1_parents[] = …; static const char * const dsp2_parents[] = …; static const char * const ipu_if_parents[] = …; static const char * const mfg_parents[] = …; static const char * const f52m_mfg_parents[] = …; static const char * const camtg_parents[] = …; static const char * const camtg2_parents[] = …; static const char * const camtg3_parents[] = …; static const char * const camtg4_parents[] = …; static const char * const uart_parents[] = …; static const char * const spi_parents[] = …; static const char * const msdc50_hclk_parents[] = …; static const char * const msdc50_0_parents[] = …; static const char * const msdc30_1_parents[] = …; static const char * const msdc30_2_parents[] = …; static const char * const audio_parents[] = …; static const char * const aud_intbus_parents[] = …; static const char * const pmicspi_parents[] = …; static const char * const fpwrap_ulposc_parents[] = …; static const char * const atb_parents[] = …; static const char * const sspm_parents[] = …; static const char * const dpi0_parents[] = …; static const char * const scam_parents[] = …; static const char * const disppwm_parents[] = …; static const char * const usb_top_parents[] = …; static const char * const ssusb_top_xhci_parents[] = …; static const char * const spm_parents[] = …; static const char * const i2c_parents[] = …; static const char * const scp_parents[] = …; static const char * const seninf_parents[] = …; static const char * const dxcc_parents[] = …; static const char * const aud_engen1_parents[] = …; static const char * const aud_engen2_parents[] = …; static const char * const faes_ufsfde_parents[] = …; static const char * const fufs_parents[] = …; static const char * const aud_1_parents[] = …; static const char * const aud_2_parents[] = …; /* * CRITICAL CLOCK: * axi_sel is the main bus clock of whole SOC. * spm_sel is the clock of the always-on co-processor. */ static const struct mtk_mux top_muxes[] = …; static const char * const apll_i2s0_parents[] = …; static const char * const apll_i2s1_parents[] = …; static const char * const apll_i2s2_parents[] = …; static const char * const apll_i2s3_parents[] = …; static const char * const apll_i2s4_parents[] = …; static const char * const apll_i2s5_parents[] = …; static const char * const mcu_mp0_parents[] = …; static const char * const mcu_mp2_parents[] = …; static const char * const mcu_bus_parents[] = …; static struct mtk_composite mcu_muxes[] = …; static struct mtk_composite top_aud_comp[] = …; static const struct mtk_gate_regs top_cg_regs = …; #define GATE_TOP(_id, _name, _parent, _shift) … static const struct mtk_gate top_clks[] = …; static const struct mtk_gate_regs infra0_cg_regs = …; static const struct mtk_gate_regs infra1_cg_regs = …; static const struct mtk_gate_regs infra2_cg_regs = …; static const struct mtk_gate_regs infra3_cg_regs = …; #define GATE_INFRA0(_id, _name, _parent, _shift) … #define GATE_INFRA1(_id, _name, _parent, _shift) … #define GATE_INFRA2(_id, _name, _parent, _shift) … #define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flag) … #define GATE_INFRA3(_id, _name, _parent, _shift) … #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) … static const struct mtk_gate infra_clks[] = …; static const struct mtk_gate_regs peri_cg_regs = …; #define GATE_PERI(_id, _name, _parent, _shift) … static const struct mtk_gate peri_clks[] = …; static u16 infra_rst_ofs[] = …; static const struct mtk_clk_rst_desc clk_rst_desc = …; /* Register mux notifier for MFG mux */ static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) { … } static const struct mtk_clk_desc infra_desc = …; static const struct mtk_clk_desc mcu_desc = …; static const struct mtk_clk_desc peri_desc = …; static const struct mtk_clk_desc topck_desc = …; static const struct of_device_id of_match_clk_mt8183[] = …; MODULE_DEVICE_TABLE(of, of_match_clk_mt8183); static struct platform_driver clk_mt8183_drv = …; module_platform_driver(…) … MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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