system_local.c | Explore in Territory

// SPDX-License-Identifier: GPL-2.0
/*
 * Support for Intel Camera Imaging ISP subsystem.
 * Copyright (c) 2015, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include "system_local.h"

/* ISP */
const hrt_address ISP_CTRL_BASE[N_ISP_ID] = …;

const hrt_address ISP_DMEM_BASE[N_ISP_ID] = …;

const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = …;

/* SP */
const hrt_address SP_CTRL_BASE[N_SP_ID] = …;

const hrt_address SP_DMEM_BASE[N_SP_ID] = …;

/* MMU */
/*
 * MMU0_ID: The data MMU
 * MMU1_ID: The icache MMU
 */
const hrt_address MMU_BASE[N_MMU_ID] = …;

/* DMA */
const hrt_address DMA_BASE[N_DMA_ID] = …;

const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = …;

/* IRQ */
const hrt_address IRQ_BASE[N_IRQ_ID] = …;

/*
	0x0000000000000500ULL};
 */

/* GDC */
const hrt_address GDC_BASE[N_GDC_ID] = …;

/* FIFO_MONITOR (not a subset of GP_DEVICE) */
const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = …;

/*
const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
	0x0000000000000000ULL};

const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
	0x0000000000090000ULL};
*/

/* GP_DEVICE (single base for all separate GP_REG instances) */
const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = …;

/*GP TIMER , all timer registers are inter-twined,
 * so, having multiple base addresses for
 * different timers does not help*/
const hrt_address GP_TIMER_BASE = …;

/* GPIO */
const hrt_address GPIO_BASE[N_GPIO_ID] = …;

/* TIMED_CTRL */
const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = …;

/* INPUT_FORMATTER */
const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = …; /* memcpy() */

/* INPUT_SYSTEM */
const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = …;

/*	0x0000000000081000ULL, */ /* capture A */
/*	0x0000000000082000ULL, */ /* capture B */
/*	0x0000000000083000ULL, */ /* capture C */
/*	0x0000000000084000ULL, */ /* Acquisition */
/*	0x0000000000085000ULL, */ /* DMA */
/*	0x0000000000089000ULL, */ /* ctrl */
/*	0x000000000008A000ULL, */ /* GP regs */
/*	0x000000000008B000ULL, */ /* FIFO */
/*	0x000000000008C000ULL, */ /* IRQ */

/* RX, the MIPI lane control regs start at offset 0 */
const hrt_address RX_BASE[N_RX_ID] = …;

/* IBUF_CTRL, part of the Input System 2401 */
const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = …;

/* ISYS IRQ Controllers, part of the Input System 2401 */
const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = …;

/* CSI FE, part of the Input System 2401 */
const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = …;

/* CSI BE, part of the Input System 2401 */
const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = …;

/* PIXEL Generator, part of the Input System 2401 */
const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = …;

/* Stream2MMIO, part of the Input System 2401 */
const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = …;
linux/drivers/staging/media/atomisp/pci/system_local.c
