/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015 Amlogic, Inc. All rights reserved. */ #ifndef __MESON_VDEC_HEVC_REGS_H_ #define __MESON_VDEC_HEVC_REGS_H_ #define HEVC_ASSIST_MMU_MAP_ADDR … #define HEVC_ASSIST_MBOX1_CLR_REG … #define HEVC_ASSIST_MBOX1_MASK … #define HEVC_ASSIST_SCRATCH_0 … #define HEVC_ASSIST_SCRATCH_1 … #define HEVC_ASSIST_SCRATCH_2 … #define HEVC_ASSIST_SCRATCH_3 … #define HEVC_ASSIST_SCRATCH_4 … #define HEVC_ASSIST_SCRATCH_5 … #define HEVC_ASSIST_SCRATCH_6 … #define HEVC_ASSIST_SCRATCH_7 … #define HEVC_ASSIST_SCRATCH_8 … #define HEVC_ASSIST_SCRATCH_9 … #define HEVC_ASSIST_SCRATCH_A … #define HEVC_ASSIST_SCRATCH_B … #define HEVC_ASSIST_SCRATCH_C … #define HEVC_ASSIST_SCRATCH_D … #define HEVC_ASSIST_SCRATCH_E … #define HEVC_ASSIST_SCRATCH_F … #define HEVC_ASSIST_SCRATCH_G … #define HEVC_ASSIST_SCRATCH_H … #define HEVC_ASSIST_SCRATCH_I … #define HEVC_ASSIST_SCRATCH_J … #define HEVC_ASSIST_SCRATCH_K … #define HEVC_ASSIST_SCRATCH_L … #define HEVC_ASSIST_SCRATCH_M … #define HEVC_ASSIST_SCRATCH_N … #define HEVC_PARSER_VERSION … #define HEVC_STREAM_CONTROL … #define HEVC_STREAM_START_ADDR … #define HEVC_STREAM_END_ADDR … #define HEVC_STREAM_WR_PTR … #define HEVC_STREAM_RD_PTR … #define HEVC_STREAM_LEVEL … #define HEVC_STREAM_FIFO_CTL … #define HEVC_SHIFT_CONTROL … #define HEVC_SHIFT_STARTCODE … #define HEVC_SHIFT_EMULATECODE … #define HEVC_SHIFT_STATUS … #define HEVC_SHIFTED_DATA … #define HEVC_SHIFT_BYTE_COUNT … #define HEVC_SHIFT_COMMAND … #define HEVC_ELEMENT_RESULT … #define HEVC_CABAC_CONTROL … #define HEVC_PARSER_SLICE_INFO … #define HEVC_PARSER_CMD_WRITE … #define HEVC_PARSER_CORE_CONTROL … #define HEVC_PARSER_CMD_FETCH … #define HEVC_PARSER_CMD_STATUS … #define HEVC_PARSER_LCU_INFO … #define HEVC_PARSER_HEADER_INFO … #define HEVC_PARSER_INT_CONTROL … #define HEVC_PARSER_INT_STATUS … #define HEVC_PARSER_IF_CONTROL … #define HEVC_PARSER_PICTURE_SIZE … #define HEVC_PARSER_LCU_START … #define HEVC_PARSER_HEADER_INFO2 … #define HEVC_PARSER_QUANT_READ … #define HEVC_PARSER_RESERVED_27 … #define HEVC_PARSER_CMD_SKIP_0 … #define HEVC_PARSER_CMD_SKIP_1 … #define HEVC_PARSER_CMD_SKIP_2 … #define HEVC_SAO_IF_STATUS … #define HEVC_SAO_IF_DATA_Y … #define HEVC_SAO_IF_DATA_U … #define HEVC_SAO_IF_DATA_V … #define HEVC_STREAM_SWAP_ADDR … #define HEVC_STREAM_SWAP_CTRL … #define HEVC_IQIT_IF_WAIT_CNT … #define HEVC_MPRED_IF_WAIT_CNT … #define HEVC_SAO_IF_WAIT_CNT … #define HEVC_MPRED_VERSION … #define HEVC_MPRED_CTRL0 … #define MPRED_CTRL0_NEW_PIC … #define MPRED_CTRL0_NEW_TILE … #define MPRED_CTRL0_NEW_SLI_SEG … #define MPRED_CTRL0_TMVP … #define MPRED_CTRL0_LDC … #define MPRED_CTRL0_COL_FROM_L0 … #define MPRED_CTRL0_ABOVE_EN … #define MPRED_CTRL0_MV_WR_EN … #define MPRED_CTRL0_MV_RD_EN … #define MPRED_CTRL0_BUF_LINEAR … #define HEVC_MPRED_CTRL1 … #define HEVC_MPRED_INT_EN … #define HEVC_MPRED_INT_STATUS … #define HEVC_MPRED_PIC_SIZE … #define HEVC_MPRED_PIC_SIZE_LCU … #define HEVC_MPRED_TILE_START … #define HEVC_MPRED_TILE_SIZE_LCU … #define HEVC_MPRED_REF_NUM … #define HEVC_MPRED_REF_EN_L0 … #define HEVC_MPRED_REF_EN_L1 … #define HEVC_MPRED_COLREF_EN_L0 … #define HEVC_MPRED_COLREF_EN_L1 … #define HEVC_MPRED_AXI_WCTRL … #define HEVC_MPRED_AXI_RCTRL … #define HEVC_MPRED_ABV_START_ADDR … #define HEVC_MPRED_MV_WR_START_ADDR … #define HEVC_MPRED_MV_RD_START_ADDR … #define HEVC_MPRED_MV_WPTR … #define HEVC_MPRED_MV_RPTR … #define HEVC_MPRED_MV_WR_ROW_JUMP … #define HEVC_MPRED_MV_RD_ROW_JUMP … #define HEVC_MPRED_CURR_LCU … #define HEVC_MPRED_ABV_WPTR … #define HEVC_MPRED_ABV_RPTR … #define HEVC_MPRED_CTRL2 … #define HEVC_MPRED_CTRL3 … #define HEVC_MPRED_L0_REF00_POC … #define HEVC_MPRED_L1_REF00_POC … #define HEVC_MPRED_CTRL4 … #define HEVC_MPRED_CUR_POC … #define HEVC_MPRED_COL_POC … #define HEVC_MPRED_MV_RD_END_ADDR … #define HEVC_MSP … #define HEVC_MPSR … #define HEVC_MCPU_INTR_MSK … #define HEVC_MCPU_INTR_REQ … #define HEVC_CPSR … #define HEVC_IMEM_DMA_CTRL … #define HEVC_IMEM_DMA_ADR … #define HEVC_IMEM_DMA_COUNT … #define HEVCD_IPP_TOP_CNTL … #define HEVCD_IPP_LINEBUFF_BASE … #define HEVCD_IPP_AXIIF_CONFIG … #define VP9D_MPP_REF_SCALE_ENBL … #define VP9D_MPP_REFINFO_TBL_ACCCONFIG … #define VP9D_MPP_REFINFO_DATA … #define HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR … #define HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR … #define HEVCD_MPP_ANC2AXI_TBL_DATA … #define HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR … #define HEVCD_MPP_ANC_CANVAS_DATA_ADDR … #define HEVCD_MPP_DECOMP_CTL1 … #define HEVCD_MPP_DECOMP_CTL2 … #define HEVCD_MCRCC_CTL1 … #define HEVCD_MCRCC_CTL2 … #define HEVCD_MCRCC_CTL3 … #define HEVC_DBLK_CFG0 … #define HEVC_DBLK_CFG1 … #define HEVC_DBLK_CFG2 … #define HEVC_DBLK_CFG3 … #define HEVC_DBLK_CFG4 … #define HEVC_DBLK_CFG5 … #define HEVC_DBLK_CFG6 … #define HEVC_DBLK_CFG7 … #define HEVC_DBLK_CFG8 … #define HEVC_DBLK_CFG9 … #define HEVC_DBLK_CFGA … #define HEVC_DBLK_STS0 … #define HEVC_DBLK_CFGB … #define HEVC_DBLK_STS1 … #define HEVC_DBLK_CFGE … #define HEVC_SAO_VERSION … #define HEVC_SAO_CTRL0 … #define HEVC_SAO_CTRL1 … #define HEVC_SAO_PIC_SIZE … #define HEVC_SAO_PIC_SIZE_LCU … #define HEVC_SAO_TILE_START … #define HEVC_SAO_TILE_SIZE_LCU … #define HEVC_SAO_Y_START_ADDR … #define HEVC_SAO_Y_LENGTH … #define HEVC_SAO_C_START_ADDR … #define HEVC_SAO_C_LENGTH … #define HEVC_SAO_Y_WPTR … #define HEVC_SAO_C_WPTR … #define HEVC_SAO_ABV_START_ADDR … #define HEVC_SAO_VB_WR_START_ADDR … #define HEVC_SAO_VB_RD_START_ADDR … #define HEVC_SAO_ABV_WPTR … #define HEVC_SAO_ABV_RPTR … #define HEVC_SAO_VB_WPTR … #define HEVC_SAO_VB_RPTR … #define HEVC_SAO_CTRL2 … #define HEVC_SAO_CTRL3 … #define HEVC_SAO_CTRL4 … #define HEVC_SAO_CTRL5 … #define HEVC_SAO_CTRL6 … #define HEVC_SAO_CTRL7 … #define HEVC_CM_BODY_START_ADDR … #define HEVC_CM_BODY_LENGTH … #define HEVC_CM_HEADER_START_ADDR … #define HEVC_CM_HEADER_LENGTH … #define HEVC_CM_HEADER_OFFSET … #define HEVC_SAO_MMU_VH0_ADDR … #define HEVC_SAO_MMU_VH1_ADDR … #define HEVC_IQIT_CLK_RST_CTRL … #define HEVC_IQIT_SCALELUT_WR_ADDR … #define HEVC_IQIT_SCALELUT_RD_ADDR … #define HEVC_IQIT_SCALELUT_DATA … #define HEVC_PSCALE_CTRL … #endif
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