/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ /* * Copyright (c) 2022 MediaTek Inc. * Author: Chun-Jie Chen <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT8186_H #define _DT_BINDINGS_CLK_MT8186_H /* MCUSYS */ #define CLK_MCU_ARMPLL_LL_SEL … #define CLK_MCU_ARMPLL_BL_SEL … #define CLK_MCU_ARMPLL_BUS_SEL … #define CLK_MCU_NR_CLK … /* TOPCKGEN */ #define CLK_TOP_AXI … #define CLK_TOP_SCP … #define CLK_TOP_MFG … #define CLK_TOP_CAMTG … #define CLK_TOP_CAMTG1 … #define CLK_TOP_CAMTG2 … #define CLK_TOP_CAMTG3 … #define CLK_TOP_CAMTG4 … #define CLK_TOP_CAMTG5 … #define CLK_TOP_CAMTG6 … #define CLK_TOP_UART … #define CLK_TOP_SPI … #define CLK_TOP_MSDC50_0_HCLK … #define CLK_TOP_MSDC50_0 … #define CLK_TOP_MSDC30_1 … #define CLK_TOP_AUDIO … #define CLK_TOP_AUD_INTBUS … #define CLK_TOP_AUD_1 … #define CLK_TOP_AUD_2 … #define CLK_TOP_AUD_ENGEN1 … #define CLK_TOP_AUD_ENGEN2 … #define CLK_TOP_DISP_PWM … #define CLK_TOP_SSPM … #define CLK_TOP_DXCC … #define CLK_TOP_USB_TOP … #define CLK_TOP_SRCK … #define CLK_TOP_SPM … #define CLK_TOP_I2C … #define CLK_TOP_PWM … #define CLK_TOP_SENINF … #define CLK_TOP_SENINF1 … #define CLK_TOP_SENINF2 … #define CLK_TOP_SENINF3 … #define CLK_TOP_AES_MSDCFDE … #define CLK_TOP_PWRAP_ULPOSC … #define CLK_TOP_CAMTM … #define CLK_TOP_VENC … #define CLK_TOP_CAM … #define CLK_TOP_IMG1 … #define CLK_TOP_IPE … #define CLK_TOP_DPMAIF … #define CLK_TOP_VDEC … #define CLK_TOP_DISP … #define CLK_TOP_MDP … #define CLK_TOP_AUDIO_H … #define CLK_TOP_UFS … #define CLK_TOP_AES_FDE … #define CLK_TOP_AUDIODSP … #define CLK_TOP_DVFSRC … #define CLK_TOP_DSI_OCC … #define CLK_TOP_SPMI_MST … #define CLK_TOP_SPINOR … #define CLK_TOP_NNA … #define CLK_TOP_NNA1 … #define CLK_TOP_NNA2 … #define CLK_TOP_SSUSB_XHCI … #define CLK_TOP_SSUSB_TOP_1P … #define CLK_TOP_SSUSB_XHCI_1P … #define CLK_TOP_WPE … #define CLK_TOP_DPI … #define CLK_TOP_U3_OCC_250M … #define CLK_TOP_U3_OCC_500M … #define CLK_TOP_ADSP_BUS … #define CLK_TOP_APLL_I2S0_MCK_SEL … #define CLK_TOP_APLL_I2S1_MCK_SEL … #define CLK_TOP_APLL_I2S2_MCK_SEL … #define CLK_TOP_APLL_I2S4_MCK_SEL … #define CLK_TOP_APLL_TDMOUT_MCK_SEL … #define CLK_TOP_MAINPLL_D2 … #define CLK_TOP_MAINPLL_D2_D2 … #define CLK_TOP_MAINPLL_D2_D4 … #define CLK_TOP_MAINPLL_D2_D16 … #define CLK_TOP_MAINPLL_D3 … #define CLK_TOP_MAINPLL_D3_D2 … #define CLK_TOP_MAINPLL_D3_D4 … #define CLK_TOP_MAINPLL_D5 … #define CLK_TOP_MAINPLL_D5_D2 … #define CLK_TOP_MAINPLL_D5_D4 … #define CLK_TOP_MAINPLL_D7 … #define CLK_TOP_MAINPLL_D7_D2 … #define CLK_TOP_MAINPLL_D7_D4 … #define CLK_TOP_UNIVPLL … #define CLK_TOP_UNIVPLL_D2 … #define CLK_TOP_UNIVPLL_D2_D2 … #define CLK_TOP_UNIVPLL_D2_D4 … #define CLK_TOP_UNIVPLL_D3 … #define CLK_TOP_UNIVPLL_D3_D2 … #define CLK_TOP_UNIVPLL_D3_D4 … #define CLK_TOP_UNIVPLL_D3_D8 … #define CLK_TOP_UNIVPLL_D3_D32 … #define CLK_TOP_UNIVPLL_D5 … #define CLK_TOP_UNIVPLL_D5_D2 … #define CLK_TOP_UNIVPLL_D5_D4 … #define CLK_TOP_UNIVPLL_D7 … #define CLK_TOP_UNIVPLL_192M … #define CLK_TOP_UNIVPLL_192M_D4 … #define CLK_TOP_UNIVPLL_192M_D8 … #define CLK_TOP_UNIVPLL_192M_D16 … #define CLK_TOP_UNIVPLL_192M_D32 … #define CLK_TOP_APLL1_D2 … #define CLK_TOP_APLL1_D4 … #define CLK_TOP_APLL1_D8 … #define CLK_TOP_APLL2_D2 … #define CLK_TOP_APLL2_D4 … #define CLK_TOP_APLL2_D8 … #define CLK_TOP_MMPLL_D2 … #define CLK_TOP_TVDPLL_D2 … #define CLK_TOP_TVDPLL_D4 … #define CLK_TOP_TVDPLL_D8 … #define CLK_TOP_TVDPLL_D16 … #define CLK_TOP_TVDPLL_D32 … #define CLK_TOP_MSDCPLL_D2 … #define CLK_TOP_ULPOSC1 … #define CLK_TOP_ULPOSC1_D2 … #define CLK_TOP_ULPOSC1_D4 … #define CLK_TOP_ULPOSC1_D8 … #define CLK_TOP_ULPOSC1_D10 … #define CLK_TOP_ULPOSC1_D16 … #define CLK_TOP_ULPOSC1_D32 … #define CLK_TOP_ADSPPLL_D2 … #define CLK_TOP_ADSPPLL_D4 … #define CLK_TOP_ADSPPLL_D8 … #define CLK_TOP_NNAPLL_D2 … #define CLK_TOP_NNAPLL_D4 … #define CLK_TOP_NNAPLL_D8 … #define CLK_TOP_NNA2PLL_D2 … #define CLK_TOP_NNA2PLL_D4 … #define CLK_TOP_NNA2PLL_D8 … #define CLK_TOP_F_BIST2FPC … #define CLK_TOP_466M_FMEM … #define CLK_TOP_MPLL … #define CLK_TOP_APLL12_CK_DIV0 … #define CLK_TOP_APLL12_CK_DIV1 … #define CLK_TOP_APLL12_CK_DIV2 … #define CLK_TOP_APLL12_CK_DIV4 … #define CLK_TOP_APLL12_CK_DIV_TDMOUT_M … #define CLK_TOP_NR_CLK … /* INFRACFG_AO */ #define CLK_INFRA_AO_PMIC_TMR … #define CLK_INFRA_AO_PMIC_AP … #define CLK_INFRA_AO_PMIC_MD … #define CLK_INFRA_AO_PMIC_CONN … #define CLK_INFRA_AO_SCP_CORE … #define CLK_INFRA_AO_SEJ … #define CLK_INFRA_AO_APXGPT … #define CLK_INFRA_AO_ICUSB … #define CLK_INFRA_AO_GCE … #define CLK_INFRA_AO_THERM … #define CLK_INFRA_AO_I2C_AP … #define CLK_INFRA_AO_I2C_CCU … #define CLK_INFRA_AO_I2C_SSPM … #define CLK_INFRA_AO_I2C_RSV … #define CLK_INFRA_AO_PWM_HCLK … #define CLK_INFRA_AO_PWM1 … #define CLK_INFRA_AO_PWM2 … #define CLK_INFRA_AO_PWM3 … #define CLK_INFRA_AO_PWM4 … #define CLK_INFRA_AO_PWM5 … #define CLK_INFRA_AO_PWM … #define CLK_INFRA_AO_UART0 … #define CLK_INFRA_AO_UART1 … #define CLK_INFRA_AO_UART2 … #define CLK_INFRA_AO_GCE_26M … #define CLK_INFRA_AO_CQ_DMA_FPC … #define CLK_INFRA_AO_BTIF … #define CLK_INFRA_AO_SPI0 … #define CLK_INFRA_AO_MSDC0 … #define CLK_INFRA_AO_MSDCFDE … #define CLK_INFRA_AO_MSDC1 … #define CLK_INFRA_AO_DVFSRC … #define CLK_INFRA_AO_GCPU … #define CLK_INFRA_AO_TRNG … #define CLK_INFRA_AO_AUXADC … #define CLK_INFRA_AO_CPUM … #define CLK_INFRA_AO_CCIF1_AP … #define CLK_INFRA_AO_CCIF1_MD … #define CLK_INFRA_AO_AUXADC_MD … #define CLK_INFRA_AO_AP_DMA … #define CLK_INFRA_AO_XIU … #define CLK_INFRA_AO_DEVICE_APC … #define CLK_INFRA_AO_CCIF_AP … #define CLK_INFRA_AO_DEBUGTOP … #define CLK_INFRA_AO_AUDIO … #define CLK_INFRA_AO_CCIF_MD … #define CLK_INFRA_AO_DXCC_SEC_CORE … #define CLK_INFRA_AO_DXCC_AO … #define CLK_INFRA_AO_IMP_IIC … #define CLK_INFRA_AO_DRAMC_F26M … #define CLK_INFRA_AO_RG_PWM_FBCLK6 … #define CLK_INFRA_AO_SSUSB_TOP_HCLK … #define CLK_INFRA_AO_DISP_PWM … #define CLK_INFRA_AO_CLDMA_BCLK … #define CLK_INFRA_AO_AUDIO_26M_BCLK … #define CLK_INFRA_AO_SSUSB_TOP_P1_HCLK … #define CLK_INFRA_AO_SPI1 … #define CLK_INFRA_AO_I2C4 … #define CLK_INFRA_AO_MODEM_TEMP_SHARE … #define CLK_INFRA_AO_SPI2 … #define CLK_INFRA_AO_SPI3 … #define CLK_INFRA_AO_SSUSB_TOP_REF … #define CLK_INFRA_AO_SSUSB_TOP_XHCI … #define CLK_INFRA_AO_SSUSB_TOP_P1_REF … #define CLK_INFRA_AO_SSUSB_TOP_P1_XHCI … #define CLK_INFRA_AO_SSPM … #define CLK_INFRA_AO_SSUSB_TOP_P1_SYS … #define CLK_INFRA_AO_I2C5 … #define CLK_INFRA_AO_I2C5_ARBITER … #define CLK_INFRA_AO_I2C5_IMM … #define CLK_INFRA_AO_I2C1_ARBITER … #define CLK_INFRA_AO_I2C1_IMM … #define CLK_INFRA_AO_I2C2_ARBITER … #define CLK_INFRA_AO_I2C2_IMM … #define CLK_INFRA_AO_SPI4 … #define CLK_INFRA_AO_SPI5 … #define CLK_INFRA_AO_CQ_DMA … #define CLK_INFRA_AO_BIST2FPC … #define CLK_INFRA_AO_MSDC0_SELF … #define CLK_INFRA_AO_SPINOR … #define CLK_INFRA_AO_SSPM_26M_SELF … #define CLK_INFRA_AO_SSPM_32K_SELF … #define CLK_INFRA_AO_I2C6 … #define CLK_INFRA_AO_AP_MSDC0 … #define CLK_INFRA_AO_MD_MSDC0 … #define CLK_INFRA_AO_MSDC0_SRC … #define CLK_INFRA_AO_MSDC1_SRC … #define CLK_INFRA_AO_SEJ_F13M … #define CLK_INFRA_AO_AES_TOP0_BCLK … #define CLK_INFRA_AO_MCU_PM_BCLK … #define CLK_INFRA_AO_CCIF2_AP … #define CLK_INFRA_AO_CCIF2_MD … #define CLK_INFRA_AO_CCIF3_AP … #define CLK_INFRA_AO_CCIF3_MD … #define CLK_INFRA_AO_FADSP_26M … #define CLK_INFRA_AO_FADSP_32K … #define CLK_INFRA_AO_CCIF4_AP … #define CLK_INFRA_AO_CCIF4_MD … #define CLK_INFRA_AO_FADSP … #define CLK_INFRA_AO_FLASHIF_133M … #define CLK_INFRA_AO_FLASHIF_66M … #define CLK_INFRA_AO_NR_CLK … /* APMIXEDSYS */ #define CLK_APMIXED_ARMPLL_LL … #define CLK_APMIXED_ARMPLL_BL … #define CLK_APMIXED_CCIPLL … #define CLK_APMIXED_MAINPLL … #define CLK_APMIXED_UNIV2PLL … #define CLK_APMIXED_MSDCPLL … #define CLK_APMIXED_MMPLL … #define CLK_APMIXED_NNAPLL … #define CLK_APMIXED_NNA2PLL … #define CLK_APMIXED_ADSPPLL … #define CLK_APMIXED_MFGPLL … #define CLK_APMIXED_TVDPLL … #define CLK_APMIXED_APLL1 … #define CLK_APMIXED_APLL2 … #define CLK_APMIXED_NR_CLK … /* IMP_IIC_WRAP */ #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 … #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 … #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 … #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 … #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 … #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 … #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 … #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 … #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 … #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 … #define CLK_IMP_IIC_WRAP_NR_CLK … /* MFGCFG */ #define CLK_MFG_BG3D … #define CLK_MFG_NR_CLK … /* MMSYS */ #define CLK_MM_DISP_MUTEX0 … #define CLK_MM_APB_MM_BUS … #define CLK_MM_DISP_OVL0 … #define CLK_MM_DISP_RDMA0 … #define CLK_MM_DISP_OVL0_2L … #define CLK_MM_DISP_WDMA0 … #define CLK_MM_DISP_RSZ0 … #define CLK_MM_DISP_AAL0 … #define CLK_MM_DISP_CCORR0 … #define CLK_MM_DISP_COLOR0 … #define CLK_MM_SMI_INFRA … #define CLK_MM_DISP_DSC_WRAP0 … #define CLK_MM_DISP_GAMMA0 … #define CLK_MM_DISP_POSTMASK0 … #define CLK_MM_DISP_DITHER0 … #define CLK_MM_SMI_COMMON … #define CLK_MM_DSI0 … #define CLK_MM_DISP_FAKE_ENG0 … #define CLK_MM_DISP_FAKE_ENG1 … #define CLK_MM_SMI_GALS … #define CLK_MM_SMI_IOMMU … #define CLK_MM_DISP_RDMA1 … #define CLK_MM_DISP_DPI … #define CLK_MM_DSI0_DSI_CK_DOMAIN … #define CLK_MM_DISP_26M … #define CLK_MM_NR_CLK … /* WPESYS */ #define CLK_WPE_CK_EN … #define CLK_WPE_SMI_LARB8_CK_EN … #define CLK_WPE_SYS_EVENT_TX_CK_EN … #define CLK_WPE_SMI_LARB8_PCLK_EN … #define CLK_WPE_NR_CLK … /* IMGSYS1 */ #define CLK_IMG1_LARB9_IMG1 … #define CLK_IMG1_LARB10_IMG1 … #define CLK_IMG1_DIP … #define CLK_IMG1_GALS_IMG1 … #define CLK_IMG1_NR_CLK … /* IMGSYS2 */ #define CLK_IMG2_LARB9_IMG2 … #define CLK_IMG2_LARB10_IMG2 … #define CLK_IMG2_MFB … #define CLK_IMG2_WPE … #define CLK_IMG2_MSS … #define CLK_IMG2_GALS_IMG2 … #define CLK_IMG2_NR_CLK … /* VDECSYS */ #define CLK_VDEC_LARB1_CKEN … #define CLK_VDEC_LAT_CKEN … #define CLK_VDEC_LAT_ACTIVE … #define CLK_VDEC_LAT_CKEN_ENG … #define CLK_VDEC_MINI_MDP_CKEN_CFG_RG … #define CLK_VDEC_CKEN … #define CLK_VDEC_ACTIVE … #define CLK_VDEC_CKEN_ENG … #define CLK_VDEC_NR_CLK … /* VENCSYS */ #define CLK_VENC_CKE0_LARB … #define CLK_VENC_CKE1_VENC … #define CLK_VENC_CKE2_JPGENC … #define CLK_VENC_CKE5_GALS … #define CLK_VENC_NR_CLK … /* CAMSYS */ #define CLK_CAM_LARB13 … #define CLK_CAM_DFP_VAD … #define CLK_CAM_LARB14 … #define CLK_CAM … #define CLK_CAMTG … #define CLK_CAM_SENINF … #define CLK_CAMSV1 … #define CLK_CAMSV2 … #define CLK_CAMSV3 … #define CLK_CAM_CCU0 … #define CLK_CAM_CCU1 … #define CLK_CAM_MRAW0 … #define CLK_CAM_FAKE_ENG … #define CLK_CAM_CCU_GALS … #define CLK_CAM2MM_GALS … #define CLK_CAM_NR_CLK … /* CAMSYS_RAWA */ #define CLK_CAM_RAWA_LARBX_RAWA … #define CLK_CAM_RAWA … #define CLK_CAM_RAWA_CAMTG_RAWA … #define CLK_CAM_RAWA_NR_CLK … /* CAMSYS_RAWB */ #define CLK_CAM_RAWB_LARBX_RAWB … #define CLK_CAM_RAWB … #define CLK_CAM_RAWB_CAMTG_RAWB … #define CLK_CAM_RAWB_NR_CLK … /* MDPSYS */ #define CLK_MDP_RDMA0 … #define CLK_MDP_TDSHP0 … #define CLK_MDP_IMG_DL_ASYNC0 … #define CLK_MDP_IMG_DL_ASYNC1 … #define CLK_MDP_DISP_RDMA … #define CLK_MDP_HMS … #define CLK_MDP_SMI0 … #define CLK_MDP_APB_BUS … #define CLK_MDP_WROT0 … #define CLK_MDP_RSZ0 … #define CLK_MDP_HDR0 … #define CLK_MDP_MUTEX0 … #define CLK_MDP_WROT1 … #define CLK_MDP_RSZ1 … #define CLK_MDP_FAKE_ENG0 … #define CLK_MDP_AAL0 … #define CLK_MDP_DISP_WDMA … #define CLK_MDP_COLOR … #define CLK_MDP_IMG_DL_ASYNC2 … #define CLK_MDP_IMG_DL_RELAY0_ASYNC0 … #define CLK_MDP_IMG_DL_RELAY1_ASYNC1 … #define CLK_MDP_IMG_DL_RELAY2_ASYNC2 … #define CLK_MDP_NR_CLK … /* IPESYS */ #define CLK_IPE_LARB19 … #define CLK_IPE_LARB20 … #define CLK_IPE_SMI_SUBCOM … #define CLK_IPE_FD … #define CLK_IPE_FE … #define CLK_IPE_RSC … #define CLK_IPE_DPE … #define CLK_IPE_GALS_IPE … #define CLK_IPE_NR_CLK … #endif /* _DT_BINDINGS_CLK_MT8186_H */
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