/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ /* * Copyright (c) 2022 MediaTek Inc. * Author: Runyang Chen <[email protected]> */ #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186 #define _DT_BINDINGS_RESET_CONTROLLER_MT8186 /* TOPRGU resets */ #define MT8186_TOPRGU_INFRA_SW_RST … #define MT8186_TOPRGU_MM_SW_RST … #define MT8186_TOPRGU_MFG_SW_RST … #define MT8186_TOPRGU_VENC_SW_RST … #define MT8186_TOPRGU_VDEC_SW_RST … #define MT8186_TOPRGU_IMG_SW_RST … #define MT8186_TOPRGU_DDR_SW_RST … #define MT8186_TOPRGU_INFRA_AO_SW_RST … #define MT8186_TOPRGU_CONNSYS_SW_RST … #define MT8186_TOPRGU_APMIXED_SW_RST … #define MT8186_TOPRGU_PWRAP_SW_RST … #define MT8186_TOPRGU_CONN_MCU_SW_RST … #define MT8186_TOPRGU_IPNNA_SW_RST … #define MT8186_TOPRGU_WPE_SW_RST … #define MT8186_TOPRGU_ADSP_SW_RST … #define MT8186_TOPRGU_AUDIO_SW_RST … #define MT8186_TOPRGU_CAM_MAIN_SW_RST … #define MT8186_TOPRGU_CAM_RAWA_SW_RST … #define MT8186_TOPRGU_CAM_RAWB_SW_RST … #define MT8186_TOPRGU_IPE_SW_RST … #define MT8186_TOPRGU_IMG2_SW_RST … #define MT8186_TOPRGU_SW_RST_NUM … /* MMSYS resets */ #define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 … /* INFRA resets */ #define MT8186_INFRA_THERMAL_CTRL_RST … #define MT8186_INFRA_PTP_CTRL_RST … #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */
Codebase Browser
linux