/* SPDX-License-Identifier: GPL-2.0+ */ /* * TI OMAP4 ISS V4L2 Driver - Register defines * * Copyright (C) 2012 Texas Instruments. * * Author: Sergio Aguirre <[email protected]> */ #ifndef _OMAP4_ISS_REGS_H_ #define _OMAP4_ISS_REGS_H_ /* ISS */ #define ISS_HL_REVISION … #define ISS_HL_SYSCONFIG … #define ISS_HL_SYSCONFIG_IDLEMODE_SHIFT … #define ISS_HL_SYSCONFIG_IDLEMODE_FORCEIDLE … #define ISS_HL_SYSCONFIG_IDLEMODE_NOIDLE … #define ISS_HL_SYSCONFIG_IDLEMODE_SMARTIDLE … #define ISS_HL_SYSCONFIG_SOFTRESET … #define ISS_HL_IRQSTATUS_RAW(i) … #define ISS_HL_IRQSTATUS(i) … #define ISS_HL_IRQENABLE_SET(i) … #define ISS_HL_IRQENABLE_CLR(i) … #define ISS_HL_IRQ_HS_VS … #define ISS_HL_IRQ_SIMCOP(i) … #define ISS_HL_IRQ_BTE … #define ISS_HL_IRQ_CBUFF … #define ISS_HL_IRQ_CCP2(i) … #define ISS_HL_IRQ_CSIB … #define ISS_HL_IRQ_CSIA … #define ISS_HL_IRQ_ISP(i) … #define ISS_CTRL … #define ISS_CTRL_CLK_DIV_MASK … #define ISS_CTRL_INPUT_SEL_MASK … #define ISS_CTRL_INPUT_SEL_CSI2A … #define ISS_CTRL_INPUT_SEL_CSI2B … #define ISS_CTRL_SYNC_DETECT_VS_RAISING … #define ISS_CLKCTRL … #define ISS_CLKCTRL_VPORT2_CLK … #define ISS_CLKCTRL_VPORT1_CLK … #define ISS_CLKCTRL_VPORT0_CLK … #define ISS_CLKCTRL_CCP2 … #define ISS_CLKCTRL_CSI2_B … #define ISS_CLKCTRL_CSI2_A … #define ISS_CLKCTRL_ISP … #define ISS_CLKCTRL_SIMCOP … #define ISS_CLKSTAT … #define ISS_CLKSTAT_VPORT2_CLK … #define ISS_CLKSTAT_VPORT1_CLK … #define ISS_CLKSTAT_VPORT0_CLK … #define ISS_CLKSTAT_CCP2 … #define ISS_CLKSTAT_CSI2_B … #define ISS_CLKSTAT_CSI2_A … #define ISS_CLKSTAT_ISP … #define ISS_CLKSTAT_SIMCOP … #define ISS_PM_STATUS … #define ISS_PM_STATUS_CBUFF_PM_MASK … #define ISS_PM_STATUS_BTE_PM_MASK … #define ISS_PM_STATUS_SIMCOP_PM_MASK … #define ISS_PM_STATUS_ISP_PM_MASK … #define ISS_PM_STATUS_CCP2_PM_MASK … #define ISS_PM_STATUS_CSI2_B_PM_MASK … #define ISS_PM_STATUS_CSI2_A_PM_MASK … #define REGISTER0 … #define REGISTER0_HSCLOCKCONFIG … #define REGISTER0_THS_TERM_MASK … #define REGISTER0_THS_TERM_SHIFT … #define REGISTER0_THS_SETTLE_MASK … #define REGISTER0_THS_SETTLE_SHIFT … #define REGISTER1 … #define REGISTER1_RESET_DONE_CTRLCLK … #define REGISTER1_CLOCK_MISS_DETECTOR_STATUS … #define REGISTER1_TCLK_TERM_MASK … #define REGISTER1_TCLK_TERM_SHIFT … #define REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT … #define REGISTER1_CTRLCLK_DIV_FACTOR_MASK … #define REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT … #define REGISTER1_TCLK_SETTLE_MASK … #define REGISTER1_TCLK_SETTLE_SHIFT … #define REGISTER2 … #define CSI2_SYSCONFIG … #define CSI2_SYSCONFIG_MSTANDBY_MODE_MASK … #define CSI2_SYSCONFIG_MSTANDBY_MODE_FORCE … #define CSI2_SYSCONFIG_MSTANDBY_MODE_NO … #define CSI2_SYSCONFIG_MSTANDBY_MODE_SMART … #define CSI2_SYSCONFIG_SOFT_RESET … #define CSI2_SYSCONFIG_AUTO_IDLE … #define CSI2_SYSSTATUS … #define CSI2_SYSSTATUS_RESET_DONE … #define CSI2_IRQSTATUS … #define CSI2_IRQENABLE … /* Shared bits across CSI2_IRQENABLE and IRQSTATUS */ #define CSI2_IRQ_OCP_ERR … #define CSI2_IRQ_SHORT_PACKET … #define CSI2_IRQ_ECC_CORRECTION … #define CSI2_IRQ_ECC_NO_CORRECTION … #define CSI2_IRQ_COMPLEXIO_ERR … #define CSI2_IRQ_FIFO_OVF … #define CSI2_IRQ_CONTEXT0 … #define CSI2_CTRL … #define CSI2_CTRL_MFLAG_LEVH_MASK … #define CSI2_CTRL_MFLAG_LEVH_SHIFT … #define CSI2_CTRL_MFLAG_LEVL_MASK … #define CSI2_CTRL_MFLAG_LEVL_SHIFT … #define CSI2_CTRL_BURST_SIZE_EXPAND … #define CSI2_CTRL_VP_CLK_EN … #define CSI2_CTRL_NON_POSTED_WRITE … #define CSI2_CTRL_VP_ONLY_EN … #define CSI2_CTRL_VP_OUT_CTRL_MASK … #define CSI2_CTRL_VP_OUT_CTRL_SHIFT … #define CSI2_CTRL_DBG_EN … #define CSI2_CTRL_BURST_SIZE_MASK … #define CSI2_CTRL_ENDIANNESS … #define CSI2_CTRL_FRAME … #define CSI2_CTRL_ECC_EN … #define CSI2_CTRL_IF_EN … #define CSI2_DBG_H … #define CSI2_COMPLEXIO_CFG … #define CSI2_COMPLEXIO_CFG_RESET_CTRL … #define CSI2_COMPLEXIO_CFG_RESET_DONE … #define CSI2_COMPLEXIO_CFG_PWD_CMD_MASK … #define CSI2_COMPLEXIO_CFG_PWD_CMD_OFF … #define CSI2_COMPLEXIO_CFG_PWD_CMD_ON … #define CSI2_COMPLEXIO_CFG_PWD_CMD_ULP … #define CSI2_COMPLEXIO_CFG_PWD_STATUS_MASK … #define CSI2_COMPLEXIO_CFG_PWD_STATUS_OFF … #define CSI2_COMPLEXIO_CFG_PWD_STATUS_ON … #define CSI2_COMPLEXIO_CFG_PWD_STATUS_ULP … #define CSI2_COMPLEXIO_CFG_PWR_AUTO … #define CSI2_COMPLEXIO_CFG_DATA_POL(i) … #define CSI2_COMPLEXIO_CFG_DATA_POSITION_MASK(i) … #define CSI2_COMPLEXIO_CFG_DATA_POSITION_SHIFT(i) … #define CSI2_COMPLEXIO_CFG_CLOCK_POL … #define CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK … #define CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT … #define CSI2_COMPLEXIO_IRQSTATUS … #define CSI2_SHORT_PACKET … #define CSI2_COMPLEXIO_IRQENABLE … /* Shared bits across CSI2_COMPLEXIO_IRQENABLE and IRQSTATUS */ #define CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT … #define CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER … #define CSI2_COMPLEXIO_IRQ_STATEULPM5 … #define CSI2_COMPLEXIO_IRQ_STATEULPM4 … #define CSI2_COMPLEXIO_IRQ_STATEULPM3 … #define CSI2_COMPLEXIO_IRQ_STATEULPM2 … #define CSI2_COMPLEXIO_IRQ_STATEULPM1 … #define CSI2_COMPLEXIO_IRQ_ERRCONTROL5 … #define CSI2_COMPLEXIO_IRQ_ERRCONTROL4 … #define CSI2_COMPLEXIO_IRQ_ERRCONTROL3 … #define CSI2_COMPLEXIO_IRQ_ERRCONTROL2 … #define CSI2_COMPLEXIO_IRQ_ERRCONTROL1 … #define CSI2_COMPLEXIO_IRQ_ERRESC5 … #define CSI2_COMPLEXIO_IRQ_ERRESC4 … #define CSI2_COMPLEXIO_IRQ_ERRESC3 … #define CSI2_COMPLEXIO_IRQ_ERRESC2 … #define CSI2_COMPLEXIO_IRQ_ERRESC1 … #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5 … #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4 … #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3 … #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2 … #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1 … #define CSI2_COMPLEXIO_IRQ_ERRSOTHS5 … #define CSI2_COMPLEXIO_IRQ_ERRSOTHS4 … #define CSI2_COMPLEXIO_IRQ_ERRSOTHS3 … #define CSI2_COMPLEXIO_IRQ_ERRSOTHS2 … #define CSI2_COMPLEXIO_IRQ_ERRSOTHS1 … #define CSI2_DBG_P … #define CSI2_TIMING … #define CSI2_TIMING_FORCE_RX_MODE_IO1 … #define CSI2_TIMING_STOP_STATE_X16_IO1 … #define CSI2_TIMING_STOP_STATE_X4_IO1 … #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK … #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT … #define CSI2_CTX_CTRL1(i) … #define CSI2_CTX_CTRL1_GENERIC … #define CSI2_CTX_CTRL1_TRANSCODE … #define CSI2_CTX_CTRL1_FEC_NUMBER_MASK … #define CSI2_CTX_CTRL1_COUNT_MASK … #define CSI2_CTX_CTRL1_COUNT_SHIFT … #define CSI2_CTX_CTRL1_EOF_EN … #define CSI2_CTX_CTRL1_EOL_EN … #define CSI2_CTX_CTRL1_CS_EN … #define CSI2_CTX_CTRL1_COUNT_UNLOCK … #define CSI2_CTX_CTRL1_PING_PONG … #define CSI2_CTX_CTRL1_CTX_EN … #define CSI2_CTX_CTRL2(i) … #define CSI2_CTX_CTRL2_FRAME_MASK … #define CSI2_CTX_CTRL2_FRAME_SHIFT … #define CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT … #define CSI2_CTX_CTRL2_USER_DEF_MAP_MASK … #define CSI2_CTX_CTRL2_VIRTUAL_ID_MASK … #define CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT … #define CSI2_CTX_CTRL2_DPCM_PRED … #define CSI2_CTX_CTRL2_FORMAT_MASK … #define CSI2_CTX_CTRL2_FORMAT_SHIFT … #define CSI2_CTX_DAT_OFST(i) … #define CSI2_CTX_DAT_OFST_MASK … #define CSI2_CTX_PING_ADDR(i) … #define CSI2_CTX_PING_ADDR_MASK … #define CSI2_CTX_PONG_ADDR(i) … #define CSI2_CTX_PONG_ADDR_MASK … #define CSI2_CTX_IRQENABLE(i) … #define CSI2_CTX_IRQSTATUS(i) … #define CSI2_CTX_CTRL3(i) … #define CSI2_CTX_CTRL3_ALPHA_SHIFT … #define CSI2_CTX_CTRL3_ALPHA_MASK … /* Shared bits across CSI2_CTX_IRQENABLE and IRQSTATUS */ #define CSI2_CTX_IRQ_ECC_CORRECTION … #define CSI2_CTX_IRQ_LINE_NUMBER … #define CSI2_CTX_IRQ_FRAME_NUMBER … #define CSI2_CTX_IRQ_CS … #define CSI2_CTX_IRQ_LE … #define CSI2_CTX_IRQ_LS … #define CSI2_CTX_IRQ_FE … #define CSI2_CTX_IRQ_FS … /* ISS BTE */ #define BTE_CTRL … #define BTE_CTRL_BW_LIMITER_MASK … #define BTE_CTRL_BW_LIMITER_SHIFT … /* ISS ISP_SYS1 */ #define ISP5_REVISION … #define ISP5_SYSCONFIG … #define ISP5_SYSCONFIG_STANDBYMODE_MASK … #define ISP5_SYSCONFIG_STANDBYMODE_FORCE … #define ISP5_SYSCONFIG_STANDBYMODE_NO … #define ISP5_SYSCONFIG_STANDBYMODE_SMART … #define ISP5_SYSCONFIG_SOFTRESET … #define ISP5_IRQSTATUS(i) … #define ISP5_IRQENABLE_SET(i) … #define ISP5_IRQENABLE_CLR(i) … /* Bits shared for ISP5_IRQ* registers */ #define ISP5_IRQ_OCP_ERR … #define ISP5_IRQ_IPIPE_INT_DPC_RNEW1 … #define ISP5_IRQ_IPIPE_INT_DPC_RNEW0 … #define ISP5_IRQ_IPIPE_INT_DPC_INIT … #define ISP5_IRQ_IPIPE_INT_EOF … #define ISP5_IRQ_H3A_INT_EOF … #define ISP5_IRQ_RSZ_INT_EOF1 … #define ISP5_IRQ_RSZ_INT_EOF0 … #define ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR … #define ISP5_IRQ_RSZ_FIFO_OVF … #define ISP5_IRQ_RSZ_INT_CYC_RSZB … #define ISP5_IRQ_RSZ_INT_CYC_RSZA … #define ISP5_IRQ_RSZ_INT_DMA … #define ISP5_IRQ_RSZ_INT_LAST_PIX … #define ISP5_IRQ_RSZ_INT_REG … #define ISP5_IRQ_H3A_INT … #define ISP5_IRQ_AF_INT … #define ISP5_IRQ_AEW_INT … #define ISP5_IRQ_IPIPEIF_IRQ … #define ISP5_IRQ_IPIPE_INT_HST … #define ISP5_IRQ_IPIPE_INT_BSC … #define ISP5_IRQ_IPIPE_INT_DMA … #define ISP5_IRQ_IPIPE_INT_LAST_PIX … #define ISP5_IRQ_IPIPE_INT_REG … #define ISP5_IRQ_ISIF_INT(i) … #define ISP5_CTRL … #define ISP5_CTRL_MSTANDBY … #define ISP5_CTRL_VD_PULSE_EXT … #define ISP5_CTRL_MSTANDBY_WAIT … #define ISP5_CTRL_BL_CLK_ENABLE … #define ISP5_CTRL_ISIF_CLK_ENABLE … #define ISP5_CTRL_H3A_CLK_ENABLE … #define ISP5_CTRL_RSZ_CLK_ENABLE … #define ISP5_CTRL_IPIPE_CLK_ENABLE … #define ISP5_CTRL_IPIPEIF_CLK_ENABLE … #define ISP5_CTRL_SYNC_ENABLE … #define ISP5_CTRL_PSYNC_CLK_SEL … /* ISS ISP ISIF register offsets */ #define ISIF_SYNCEN … #define ISIF_SYNCEN_DWEN … #define ISIF_SYNCEN_SYEN … #define ISIF_MODESET … #define ISIF_MODESET_INPMOD_MASK … #define ISIF_MODESET_INPMOD_RAW … #define ISIF_MODESET_INPMOD_YCBCR16 … #define ISIF_MODESET_INPMOD_YCBCR8 … #define ISIF_MODESET_CCDW_MASK … #define ISIF_MODESET_CCDW_2BIT … #define ISIF_MODESET_CCDMD … #define ISIF_MODESET_SWEN … #define ISIF_MODESET_HDPOL … #define ISIF_MODESET_VDPOL … #define ISIF_SPH … #define ISIF_SPH_MASK … #define ISIF_LNH … #define ISIF_LNH_MASK … #define ISIF_LNV … #define ISIF_LNV_MASK … #define ISIF_HSIZE … #define ISIF_HSIZE_ADCR … #define ISIF_HSIZE_HSIZE_MASK … #define ISIF_CADU … #define ISIF_CADU_MASK … #define ISIF_CADL … #define ISIF_CADL_MASK … #define ISIF_CCOLP … #define ISIF_CCOLP_CP0_F0_R … #define ISIF_CCOLP_CP0_F0_GR … #define ISIF_CCOLP_CP0_F0_B … #define ISIF_CCOLP_CP0_F0_GB … #define ISIF_CCOLP_CP1_F0_R … #define ISIF_CCOLP_CP1_F0_GR … #define ISIF_CCOLP_CP1_F0_B … #define ISIF_CCOLP_CP1_F0_GB … #define ISIF_CCOLP_CP2_F0_R … #define ISIF_CCOLP_CP2_F0_GR … #define ISIF_CCOLP_CP2_F0_B … #define ISIF_CCOLP_CP2_F0_GB … #define ISIF_CCOLP_CP3_F0_R … #define ISIF_CCOLP_CP3_F0_GR … #define ISIF_CCOLP_CP3_F0_B … #define ISIF_CCOLP_CP3_F0_GB … #define ISIF_VDINT(i) … #define ISIF_VDINT_MASK … #define ISIF_CGAMMAWD … #define ISIF_CGAMMAWD_GWDI_MASK … #define ISIF_CGAMMAWD_GWDI(bpp) … #define ISIF_CCDCFG … #define ISIF_CCDCFG_Y8POS … /* ISS ISP IPIPEIF register offsets */ #define IPIPEIF_ENABLE … #define IPIPEIF_CFG1 … #define IPIPEIF_CFG1_INPSRC1_MASK … #define IPIPEIF_CFG1_INPSRC1_VPORT_RAW … #define IPIPEIF_CFG1_INPSRC1_SDRAM_RAW … #define IPIPEIF_CFG1_INPSRC1_ISIF_DARKFM … #define IPIPEIF_CFG1_INPSRC1_SDRAM_YUV … #define IPIPEIF_CFG1_INPSRC2_MASK … #define IPIPEIF_CFG1_INPSRC2_ISIF … #define IPIPEIF_CFG1_INPSRC2_SDRAM_RAW … #define IPIPEIF_CFG1_INPSRC2_ISIF_DARKFM … #define IPIPEIF_CFG1_INPSRC2_SDRAM_YUV … #define IPIPEIF_CFG2 … #define IPIPEIF_CFG2_YUV8P … #define IPIPEIF_CFG2_YUV8 … #define IPIPEIF_CFG2_YUV16 … #define IPIPEIF_CFG2_VDPOL … #define IPIPEIF_CFG2_HDPOL … #define IPIPEIF_CFG2_INTSW … #define IPIPEIF_CLKDIV … /* ISS ISP IPIPE register offsets */ #define IPIPE_SRC_EN … #define IPIPE_SRC_EN_EN … #define IPIPE_SRC_MODE … #define IPIPE_SRC_MODE_WRT … #define IPIPE_SRC_MODE_OST … #define IPIPE_SRC_FMT … #define IPIPE_SRC_FMT_RAW2YUV … #define IPIPE_SRC_FMT_RAW2RAW … #define IPIPE_SRC_FMT_RAW2STATS … #define IPIPE_SRC_FMT_YUV2YUV … #define IPIPE_SRC_COL … #define IPIPE_SRC_COL_OO_R … #define IPIPE_SRC_COL_OO_GR … #define IPIPE_SRC_COL_OO_B … #define IPIPE_SRC_COL_OO_GB … #define IPIPE_SRC_COL_OE_R … #define IPIPE_SRC_COL_OE_GR … #define IPIPE_SRC_COL_OE_B … #define IPIPE_SRC_COL_OE_GB … #define IPIPE_SRC_COL_EO_R … #define IPIPE_SRC_COL_EO_GR … #define IPIPE_SRC_COL_EO_B … #define IPIPE_SRC_COL_EO_GB … #define IPIPE_SRC_COL_EE_R … #define IPIPE_SRC_COL_EE_GR … #define IPIPE_SRC_COL_EE_B … #define IPIPE_SRC_COL_EE_GB … #define IPIPE_SRC_VPS … #define IPIPE_SRC_VPS_MASK … #define IPIPE_SRC_VSZ … #define IPIPE_SRC_VSZ_MASK … #define IPIPE_SRC_HPS … #define IPIPE_SRC_HPS_MASK … #define IPIPE_SRC_HSZ … #define IPIPE_SRC_HSZ_MASK … #define IPIPE_SEL_SBU … #define IPIPE_SRC_STA … #define IPIPE_GCK_MMR … #define IPIPE_GCK_MMR_REG … #define IPIPE_GCK_PIX … #define IPIPE_GCK_PIX_G3 … #define IPIPE_GCK_PIX_G2 … #define IPIPE_GCK_PIX_G1 … #define IPIPE_GCK_PIX_G0 … #define IPIPE_DPC_LUT_EN … #define IPIPE_DPC_LUT_SEL … #define IPIPE_DPC_LUT_ADR … #define IPIPE_DPC_LUT_SIZ … #define IPIPE_DPC_OTF_EN … #define IPIPE_DPC_OTF_TYP … #define IPIPE_DPC_OTF_2_D_THR_R … #define IPIPE_DPC_OTF_2_D_THR_GR … #define IPIPE_DPC_OTF_2_D_THR_GB … #define IPIPE_DPC_OTF_2_D_THR_B … #define IPIPE_DPC_OTF_2_C_THR_R … #define IPIPE_DPC_OTF_2_C_THR_GR … #define IPIPE_DPC_OTF_2_C_THR_GB … #define IPIPE_DPC_OTF_2_C_THR_B … #define IPIPE_DPC_OTF_3_SHF … #define IPIPE_DPC_OTF_3_D_THR … #define IPIPE_DPC_OTF_3_D_SPL … #define IPIPE_DPC_OTF_3_D_MIN … #define IPIPE_DPC_OTF_3_D_MAX … #define IPIPE_DPC_OTF_3_C_THR … #define IPIPE_DPC_OTF_3_C_SLP … #define IPIPE_DPC_OTF_3_C_MIN … #define IPIPE_DPC_OTF_3_C_MAX … #define IPIPE_LSC_VOFT … #define IPIPE_LSC_VA2 … #define IPIPE_LSC_VA1 … #define IPIPE_LSC_VS … #define IPIPE_LSC_HOFT … #define IPIPE_LSC_HA2 … #define IPIPE_LSC_HA1 … #define IPIPE_LSC_HS … #define IPIPE_LSC_GAN_R … #define IPIPE_LSC_GAN_GR … #define IPIPE_LSC_GAN_GB … #define IPIPE_LSC_GAN_B … #define IPIPE_LSC_OFT_R … #define IPIPE_LSC_OFT_GR … #define IPIPE_LSC_OFT_GB … #define IPIPE_LSC_OFT_B … #define IPIPE_LSC_SHF … #define IPIPE_LSC_MAX … #define IPIPE_D2F_1ST_EN … #define IPIPE_D2F_1ST_TYP … #define IPIPE_D2F_1ST_THR_00 … #define IPIPE_D2F_1ST_THR_01 … #define IPIPE_D2F_1ST_THR_02 … #define IPIPE_D2F_1ST_THR_03 … #define IPIPE_D2F_1ST_THR_04 … #define IPIPE_D2F_1ST_THR_05 … #define IPIPE_D2F_1ST_THR_06 … #define IPIPE_D2F_1ST_THR_07 … #define IPIPE_D2F_1ST_STR_00 … #define IPIPE_D2F_1ST_STR_01 … #define IPIPE_D2F_1ST_STR_02 … #define IPIPE_D2F_1ST_STR_03 … #define IPIPE_D2F_1ST_STR_04 … #define IPIPE_D2F_1ST_STR_05 … #define IPIPE_D2F_1ST_STR_06 … #define IPIPE_D2F_1ST_STR_07 … #define IPIPE_D2F_1ST_SPR_00 … #define IPIPE_D2F_1ST_SPR_01 … #define IPIPE_D2F_1ST_SPR_02 … #define IPIPE_D2F_1ST_SPR_03 … #define IPIPE_D2F_1ST_SPR_04 … #define IPIPE_D2F_1ST_SPR_05 … #define IPIPE_D2F_1ST_SPR_06 … #define IPIPE_D2F_1ST_SPR_07 … #define IPIPE_D2F_1ST_EDG_MIN … #define IPIPE_D2F_1ST_EDG_MAX … #define IPIPE_D2F_2ND_EN … #define IPIPE_D2F_2ND_TYP … #define IPIPE_D2F_2ND_THR00 … #define IPIPE_D2F_2ND_THR01 … #define IPIPE_D2F_2ND_THR02 … #define IPIPE_D2F_2ND_THR03 … #define IPIPE_D2F_2ND_THR04 … #define IPIPE_D2F_2ND_THR05 … #define IPIPE_D2F_2ND_THR06 … #define IPIPE_D2F_2ND_THR07 … #define IPIPE_D2F_2ND_STR_00 … #define IPIPE_D2F_2ND_STR_01 … #define IPIPE_D2F_2ND_STR_02 … #define IPIPE_D2F_2ND_STR_03 … #define IPIPE_D2F_2ND_STR_04 … #define IPIPE_D2F_2ND_STR_05 … #define IPIPE_D2F_2ND_STR_06 … #define IPIPE_D2F_2ND_STR_07 … #define IPIPE_D2F_2ND_SPR_00 … #define IPIPE_D2F_2ND_SPR_01 … #define IPIPE_D2F_2ND_SPR_02 … #define IPIPE_D2F_2ND_SPR_03 … #define IPIPE_D2F_2ND_SPR_04 … #define IPIPE_D2F_2ND_SPR_05 … #define IPIPE_D2F_2ND_SPR_06 … #define IPIPE_D2F_2ND_SPR_07 … #define IPIPE_D2F_2ND_EDG_MIN … #define IPIPE_D2F_2ND_EDG_MAX … #define IPIPE_GIC_EN … #define IPIPE_GIC_TYP … #define IPIPE_GIC_GAN … #define IPIPE_GIC_NFGAIN … #define IPIPE_GIC_THR … #define IPIPE_GIC_SLP … #define IPIPE_WB2_OFT_R … #define IPIPE_WB2_OFT_GR … #define IPIPE_WB2_OFT_GB … #define IPIPE_WB2_OFT_B … #define IPIPE_WB2_WGN_R … #define IPIPE_WB2_WGN_GR … #define IPIPE_WB2_WGN_GB … #define IPIPE_WB2_WGN_B … #define IPIPE_CFA_MODE … #define IPIPE_CFA_2DIR_HPF_THR … #define IPIPE_CFA_2DIR_HPF_SLP … #define IPIPE_CFA_2DIR_MIX_THR … #define IPIPE_CFA_2DIR_MIX_SLP … #define IPIPE_CFA_2DIR_DIR_TRH … #define IPIPE_CFA_2DIR_DIR_SLP … #define IPIPE_CFA_2DIR_NDWT … #define IPIPE_CFA_MONO_HUE_FRA … #define IPIPE_CFA_MONO_EDG_THR … #define IPIPE_CFA_MONO_THR_MIN … #define IPIPE_CFA_MONO_THR_SLP … #define IPIPE_CFA_MONO_SLP_MIN … #define IPIPE_CFA_MONO_SLP_SLP … #define IPIPE_CFA_MONO_LPWT … #define IPIPE_RGB1_MUL_RR … #define IPIPE_RGB1_MUL_GR … #define IPIPE_RGB1_MUL_BR … #define IPIPE_RGB1_MUL_RG … #define IPIPE_RGB1_MUL_GG … #define IPIPE_RGB1_MUL_BG … #define IPIPE_RGB1_MUL_RB … #define IPIPE_RGB1_MUL_GB … #define IPIPE_RGB1_MUL_BB … #define IPIPE_RGB1_OFT_OR … #define IPIPE_RGB1_OFT_OG … #define IPIPE_RGB1_OFT_OB … #define IPIPE_GMM_CFG … #define IPIPE_RGB2_MUL_RR … #define IPIPE_RGB2_MUL_GR … #define IPIPE_RGB2_MUL_BR … #define IPIPE_RGB2_MUL_RG … #define IPIPE_RGB2_MUL_GG … #define IPIPE_RGB2_MUL_BG … #define IPIPE_RGB2_MUL_RB … #define IPIPE_RGB2_MUL_GB … #define IPIPE_RGB2_MUL_BB … #define IPIPE_RGB2_OFT_OR … #define IPIPE_RGB2_OFT_OG … #define IPIPE_RGB2_OFT_OB … #define IPIPE_YUV_ADJ … #define IPIPE_YUV_MUL_RY … #define IPIPE_YUV_MUL_GY … #define IPIPE_YUV_MUL_BY … #define IPIPE_YUV_MUL_RCB … #define IPIPE_YUV_MUL_GCB … #define IPIPE_YUV_MUL_BCB … #define IPIPE_YUV_MUL_RCR … #define IPIPE_YUV_MUL_GCR … #define IPIPE_YUV_MUL_BCR … #define IPIPE_YUV_OFT_Y … #define IPIPE_YUV_OFT_CB … #define IPIPE_YUV_OFT_CR … #define IPIPE_YUV_PHS … #define IPIPE_YUV_PHS_LPF … #define IPIPE_YUV_PHS_POS … #define IPIPE_YEE_EN … #define IPIPE_YEE_TYP … #define IPIPE_YEE_SHF … #define IPIPE_YEE_MUL_00 … #define IPIPE_YEE_MUL_01 … #define IPIPE_YEE_MUL_02 … #define IPIPE_YEE_MUL_10 … #define IPIPE_YEE_MUL_11 … #define IPIPE_YEE_MUL_12 … #define IPIPE_YEE_MUL_20 … #define IPIPE_YEE_MUL_21 … #define IPIPE_YEE_MUL_22 … #define IPIPE_YEE_THR … #define IPIPE_YEE_E_GAN … #define IPIPE_YEE_E_THR_1 … #define IPIPE_YEE_E_THR_2 … #define IPIPE_YEE_G_GAN … #define IPIPE_YEE_G_OFT … #define IPIPE_CAR_EN … #define IPIPE_CAR_TYP … #define IPIPE_CAR_SW … #define IPIPE_CAR_HPF_TYP … #define IPIPE_CAR_HPF_SHF … #define IPIPE_CAR_HPF_THR … #define IPIPE_CAR_GN1_GAN … #define IPIPE_CAR_GN1_SHF … #define IPIPE_CAR_GN1_MIN … #define IPIPE_CAR_GN2_GAN … #define IPIPE_CAR_GN2_SHF … #define IPIPE_CAR_GN2_MIN … #define IPIPE_CGS_EN … #define IPIPE_CGS_GN1_L_THR … #define IPIPE_CGS_GN1_L_GAIN … #define IPIPE_CGS_GN1_L_SHF … #define IPIPE_CGS_GN1_L_MIN … #define IPIPE_CGS_GN1_H_THR … #define IPIPE_CGS_GN1_H_GAIN … #define IPIPE_CGS_GN1_H_SHF … #define IPIPE_CGS_GN1_H_MIN … #define IPIPE_CGS_GN2_L_THR … #define IPIPE_CGS_GN2_L_GAIN … #define IPIPE_CGS_GN2_L_SHF … #define IPIPE_CGS_GN2_L_MIN … #define IPIPE_BOX_EN … #define IPIPE_BOX_MODE … #define IPIPE_BOX_TYP … #define IPIPE_BOX_SHF … #define IPIPE_BOX_SDR_SAD_H … #define IPIPE_BOX_SDR_SAD_L … #define IPIPE_HST_EN … #define IPIPE_HST_MODE … #define IPIPE_HST_SEL … #define IPIPE_HST_PARA … #define IPIPE_HST_0_VPS … #define IPIPE_HST_0_VSZ … #define IPIPE_HST_0_HPS … #define IPIPE_HST_0_HSZ … #define IPIPE_HST_1_VPS … #define IPIPE_HST_1_VSZ … #define IPIPE_HST_1_HPS … #define IPIPE_HST_1_HSZ … #define IPIPE_HST_2_VPS … #define IPIPE_HST_2_VSZ … #define IPIPE_HST_2_HPS … #define IPIPE_HST_2_HSZ … #define IPIPE_HST_3_VPS … #define IPIPE_HST_3_VSZ … #define IPIPE_HST_3_HPS … #define IPIPE_HST_3_HSZ … #define IPIPE_HST_TBL … #define IPIPE_HST_MUL_R … #define IPIPE_HST_MUL_GR … #define IPIPE_HST_MUL_GB … #define IPIPE_HST_MUL_B … #define IPIPE_BSC_EN … #define IPIPE_BSC_MODE … #define IPIPE_BSC_TYP … #define IPIPE_BSC_ROW_VCT … #define IPIPE_BSC_ROW_SHF … #define IPIPE_BSC_ROW_VPO … #define IPIPE_BSC_ROW_VNU … #define IPIPE_BSC_ROW_VSKIP … #define IPIPE_BSC_ROW_HPO … #define IPIPE_BSC_ROW_HNU … #define IPIPE_BSC_ROW_HSKIP … #define IPIPE_BSC_COL_VCT … #define IPIPE_BSC_COL_SHF … #define IPIPE_BSC_COL_VPO … #define IPIPE_BSC_COL_VNU … #define IPIPE_BSC_COL_VSKIP … #define IPIPE_BSC_COL_HPO … #define IPIPE_BSC_COL_HNU … #define IPIPE_BSC_COL_HSKIP … #define IPIPE_BSC_EN … /* ISS ISP Resizer register offsets */ #define RSZ_REVISION … #define RSZ_SYSCONFIG … #define RSZ_SYSCONFIG_RSZB_CLK_EN … #define RSZ_SYSCONFIG_RSZA_CLK_EN … #define RSZ_IN_FIFO_CTRL … #define RSZ_IN_FIFO_CTRL_THRLD_LOW_MASK … #define RSZ_IN_FIFO_CTRL_THRLD_LOW_SHIFT … #define RSZ_IN_FIFO_CTRL_THRLD_HIGH_MASK … #define RSZ_IN_FIFO_CTRL_THRLD_HIGH_SHIFT … #define RSZ_FRACDIV … #define RSZ_FRACDIV_MASK … #define RSZ_SRC_EN … #define RSZ_SRC_EN_SRC_EN … #define RSZ_SRC_MODE … #define RSZ_SRC_MODE_OST … #define RSZ_SRC_MODE_WRT … #define RSZ_SRC_FMT0 … #define RSZ_SRC_FMT0_BYPASS … #define RSZ_SRC_FMT0_SEL … #define RSZ_SRC_FMT1 … #define RSZ_SRC_FMT1_IN420 … #define RSZ_SRC_VPS … #define RSZ_SRC_VSZ … #define RSZ_SRC_HPS … #define RSZ_SRC_HSZ … #define RSZ_DMA_RZA … #define RSZ_DMA_RZB … #define RSZ_DMA_STA … #define RSZ_GCK_MMR … #define RSZ_GCK_MMR_MMR … #define RSZ_GCK_SDR … #define RSZ_GCK_SDR_CORE … #define RSZ_IRQ_RZA … #define RSZ_IRQ_RZA_MASK … #define RSZ_IRQ_RZB … #define RSZ_IRQ_RZB_MASK … #define RSZ_YUV_Y_MIN … #define RSZ_YUV_Y_MAX … #define RSZ_YUV_C_MIN … #define RSZ_YUV_C_MAX … #define RSZ_SEQ … #define RSZ_SEQ_HRVB … #define RSZ_SEQ_HRVA … #define RZA_EN … #define RZA_MODE … #define RZA_MODE_ONE_SHOT … #define RZA_420 … #define RZA_I_VPS … #define RZA_I_HPS … #define RZA_O_VSZ … #define RZA_O_HSZ … #define RZA_V_PHS_Y … #define RZA_V_PHS_C … #define RZA_V_DIF … #define RZA_V_TYP … #define RZA_V_LPF … #define RZA_H_PHS … #define RZA_H_DIF … #define RZA_H_TYP … #define RZA_H_LPF … #define RZA_DWN_EN … #define RZA_SDR_Y_BAD_H … #define RZA_SDR_Y_BAD_L … #define RZA_SDR_Y_SAD_H … #define RZA_SDR_Y_SAD_L … #define RZA_SDR_Y_OFT … #define RZA_SDR_Y_PTR_S … #define RZA_SDR_Y_PTR_E … #define RZA_SDR_C_BAD_H … #define RZA_SDR_C_BAD_L … #define RZA_SDR_C_SAD_H … #define RZA_SDR_C_SAD_L … #define RZA_SDR_C_OFT … #define RZA_SDR_C_PTR_S … #define RZA_SDR_C_PTR_E … #define RZB_EN … #define RZB_MODE … #define RZB_420 … #define RZB_I_VPS … #define RZB_I_HPS … #define RZB_O_VSZ … #define RZB_O_HSZ … #define RZB_V_DIF … #define RZB_V_TYP … #define RZB_V_LPF … #define RZB_H_DIF … #define RZB_H_TYP … #define RZB_H_LPF … #define RZB_SDR_Y_BAD_H … #define RZB_SDR_Y_BAD_L … #define RZB_SDR_Y_SAD_H … #define RZB_SDR_Y_SAD_L … #define RZB_SDR_Y_OFT … #define RZB_SDR_Y_PTR_S … #define RZB_SDR_Y_PTR_E … #define RZB_SDR_C_BAD_H … #define RZB_SDR_C_BAD_L … #define RZB_SDR_C_SAD_H … #define RZB_SDR_C_SAD_L … #define RZB_SDR_C_PTR_S … #define RZB_SDR_C_PTR_E … /* Shared Bitmasks between RZA & RZB */ #define RSZ_EN_EN … #define RSZ_420_CEN … #define RSZ_420_YEN … #define RSZ_I_VPS_MASK … #define RSZ_I_HPS_MASK … #define RSZ_O_VSZ_MASK … #define RSZ_O_HSZ_MASK … #define RSZ_V_PHS_Y_MASK … #define RSZ_V_PHS_C_MASK … #define RSZ_V_DIF_MASK … #define RSZ_V_TYP_C … #define RSZ_V_TYP_Y … #define RSZ_V_LPF_C_MASK … #define RSZ_V_LPF_C_SHIFT … #define RSZ_V_LPF_Y_MASK … #define RSZ_V_LPF_Y_SHIFT … #define RSZ_H_PHS_MASK … #define RSZ_H_DIF_MASK … #define RSZ_H_TYP_C … #define RSZ_H_TYP_Y … #define RSZ_H_LPF_C_MASK … #define RSZ_H_LPF_C_SHIFT … #define RSZ_H_LPF_Y_MASK … #define RSZ_H_LPF_Y_SHIFT … #define RSZ_DWN_EN_DWN_EN … #endif /* _OMAP4_ISS_REGS_H_ */
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