/* * arch/arm/mach-omap2/control.h * * OMAP2/3/4 System Control Module definitions * * Copyright (C) 2007-2010 Texas Instruments, Inc. * Copyright (C) 2007-2008, 2010 Nokia Corporation * * Written by Paul Walmsley * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. */ #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H #define __ARCH_ARM_MACH_OMAP2_CONTROL_H #include "am33xx.h" #ifndef __ASSEMBLY__ #define OMAP242X_CTRL_REGADDR(reg) … #define OMAP243X_CTRL_REGADDR(reg) … #define OMAP343X_CTRL_REGADDR(reg) … #define AM33XX_CTRL_REGADDR(reg) … #else #define OMAP242X_CTRL_REGADDR … #define OMAP243X_CTRL_REGADDR … #define OMAP343X_CTRL_REGADDR … #define AM33XX_CTRL_REGADDR … #endif /* __ASSEMBLY__ */ /* * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for * OMAP24XX and OMAP34XX. */ /* Control submodule offsets */ #define OMAP2_CONTROL_INTERFACE … #define OMAP2_CONTROL_PADCONFS … #define OMAP2_CONTROL_GENERAL … #define OMAP343X_CONTROL_MEM_WKUP … #define OMAP343X_CONTROL_PADCONFS_WKUP … #define OMAP343X_CONTROL_GENERAL_WKUP … /* TI81XX spefic control submodules */ #define TI81XX_CONTROL_DEVBOOT … #define TI81XX_CONTROL_DEVCONF … /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ #define OMAP2_CONTROL_SYSCONFIG … /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ #define OMAP2_CONTROL_DEVCONF0 … #define OMAP2_CONTROL_MSUSPENDMUX_0 … #define OMAP2_CONTROL_MSUSPENDMUX_1 … #define OMAP2_CONTROL_MSUSPENDMUX_2 … #define OMAP2_CONTROL_MSUSPENDMUX_3 … #define OMAP2_CONTROL_MSUSPENDMUX_4 … #define OMAP2_CONTROL_MSUSPENDMUX_5 … #define OMAP2_CONTROL_SEC_CTRL … #define OMAP2_CONTROL_RPUB_KEY_H_0 … #define OMAP2_CONTROL_RPUB_KEY_H_1 … #define OMAP2_CONTROL_RPUB_KEY_H_2 … #define OMAP2_CONTROL_RPUB_KEY_H_3 … /* 242x-only CONTROL_GENERAL register offsets */ #define OMAP242X_CONTROL_DEVCONF … #define OMAP242X_CONTROL_OCM_RAM_PERM … /* 243x-only CONTROL_GENERAL register offsets */ /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ #define OMAP243X_CONTROL_DEVCONF1 … #define OMAP243X_CONTROL_CSIRXFE … #define OMAP243X_CONTROL_IVA2_BOOTADDR … #define OMAP243X_CONTROL_IVA2_BOOTMOD … #define OMAP243X_CONTROL_IVA2_GEMCFG … #define OMAP243X_CONTROL_PBIAS_LITE … /* 24xx-only CONTROL_GENERAL register offsets */ #define OMAP24XX_CONTROL_DEBOBS … #define OMAP24XX_CONTROL_EMU_SUPPORT … #define OMAP24XX_CONTROL_SEC_TEST … #define OMAP24XX_CONTROL_PSA_CTRL … #define OMAP24XX_CONTROL_PSA_CMD … #define OMAP24XX_CONTROL_PSA_VALUE … #define OMAP24XX_CONTROL_SEC_EMU … #define OMAP24XX_CONTROL_SEC_TAP … #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD … #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD … #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD … #define OMAP24XX_CONTROL_SEC_STATUS … #define OMAP24XX_CONTROL_SEC_ERR_STATUS … #define OMAP24XX_CONTROL_STATUS … #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS … #define OMAP24XX_CONTROL_RAND_KEY_0 … #define OMAP24XX_CONTROL_RAND_KEY_1 … #define OMAP24XX_CONTROL_RAND_KEY_2 … #define OMAP24XX_CONTROL_RAND_KEY_3 … #define OMAP24XX_CONTROL_CUST_KEY_0 … #define OMAP24XX_CONTROL_CUST_KEY_1 … #define OMAP24XX_CONTROL_TEST_KEY_0 … #define OMAP24XX_CONTROL_TEST_KEY_1 … #define OMAP24XX_CONTROL_TEST_KEY_2 … #define OMAP24XX_CONTROL_TEST_KEY_3 … #define OMAP24XX_CONTROL_TEST_KEY_4 … #define OMAP24XX_CONTROL_TEST_KEY_5 … #define OMAP24XX_CONTROL_TEST_KEY_6 … #define OMAP24XX_CONTROL_TEST_KEY_7 … #define OMAP24XX_CONTROL_TEST_KEY_8 … #define OMAP24XX_CONTROL_TEST_KEY_9 … #define OMAP343X_CONTROL_PADCONF_SYSNIRQ … /* 34xx-only CONTROL_GENERAL register offsets */ #define OMAP343X_CONTROL_PADCONF_OFF … #define OMAP343X_CONTROL_MEM_DFTRW0 … #define OMAP343X_CONTROL_MEM_DFTRW1 … #define OMAP343X_CONTROL_DEVCONF1 … #define OMAP343X_CONTROL_CSIRXFE … #define OMAP343X_CONTROL_SEC_STATUS … #define OMAP343X_CONTROL_SEC_ERR_STATUS … #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG … #define OMAP343X_CONTROL_STATUS … #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS … #define OMAP343X_CONTROL_RPUB_KEY_H_4 … #define OMAP343X_CONTROL_RAND_KEY_0 … #define OMAP343X_CONTROL_RAND_KEY_1 … #define OMAP343X_CONTROL_RAND_KEY_2 … #define OMAP343X_CONTROL_RAND_KEY_3 … #define OMAP343X_CONTROL_TEST_KEY_0 … #define OMAP343X_CONTROL_TEST_KEY_1 … #define OMAP343X_CONTROL_TEST_KEY_2 … #define OMAP343X_CONTROL_TEST_KEY_3 … #define OMAP343X_CONTROL_TEST_KEY_4 … #define OMAP343X_CONTROL_TEST_KEY_5 … #define OMAP343X_CONTROL_TEST_KEY_6 … #define OMAP343X_CONTROL_TEST_KEY_7 … #define OMAP343X_CONTROL_TEST_KEY_8 … #define OMAP343X_CONTROL_TEST_KEY_9 … #define OMAP343X_CONTROL_TEST_KEY_10 … #define OMAP343X_CONTROL_TEST_KEY_11 … #define OMAP343X_CONTROL_TEST_KEY_12 … #define OMAP343X_CONTROL_TEST_KEY_13 … #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 … #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 … #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 … #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 … #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 … #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 … #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 … #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 … #define OMAP343X_CONTROL_FUSE_SR … #define OMAP343X_CONTROL_IVA2_BOOTADDR … #define OMAP343X_CONTROL_IVA2_BOOTMOD … #define OMAP343X_CONTROL_DEBOBS(i) … #define OMAP343X_CONTROL_PROG_IO0 … #define OMAP343X_CONTROL_PROG_IO1 … #define OMAP343X_CONTROL_DSS_DPLL_SPREADING … #define OMAP343X_CONTROL_CORE_DPLL_SPREADING … #define OMAP343X_CONTROL_PER_DPLL_SPREADING … #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING … #define OMAP343X_CONTROL_PBIAS_LITE … #define OMAP343X_CONTROL_TEMP_SENSOR … #define OMAP343X_CONTROL_SRAMLDO4 … #define OMAP343X_CONTROL_SRAMLDO5 … #define OMAP343X_CONTROL_CSI … /* OMAP3630 only CONTROL_GENERAL register offsets */ #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 … #define OMAP3630_CONTROL_FUSE_OPP50_VDD1 … #define OMAP3630_CONTROL_FUSE_OPP100_VDD1 … #define OMAP3630_CONTROL_FUSE_OPP120_VDD1 … #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 … #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 … #define OMAP3630_CONTROL_CAMERA_PHY_CTRL … /* OMAP44xx control efuse offsets */ #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 … #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 … #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO … #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO … #define OMAP44XX_CONTROL_FUSE_MPU_OPP50 … #define OMAP44XX_CONTROL_FUSE_MPU_OPP100 … #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO … #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO … #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB … #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 … #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 … #define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV … /* AM35XX only CONTROL_GENERAL register offsets */ #define AM35XX_CONTROL_MSUSPENDMUX_6 … #define AM35XX_CONTROL_DEVCONF2 … #define AM35XX_CONTROL_DEVCONF3 … #define AM35XX_CONTROL_CBA_PRIORITY … #define AM35XX_CONTROL_LVL_INTR_CLEAR … #define AM35XX_CONTROL_IP_SW_RESET … #define AM35XX_CONTROL_IPSS_CLK_CTRL … /* 34xx PADCONF register offsets */ #define OMAP343X_PADCONF_ETK(i) … #define OMAP343X_PADCONF_ETK_CLK … #define OMAP343X_PADCONF_ETK_CTL … #define OMAP343X_PADCONF_ETK_D0 … #define OMAP343X_PADCONF_ETK_D1 … #define OMAP343X_PADCONF_ETK_D2 … #define OMAP343X_PADCONF_ETK_D3 … #define OMAP343X_PADCONF_ETK_D4 … #define OMAP343X_PADCONF_ETK_D5 … #define OMAP343X_PADCONF_ETK_D6 … #define OMAP343X_PADCONF_ETK_D7 … #define OMAP343X_PADCONF_ETK_D8 … #define OMAP343X_PADCONF_ETK_D9 … #define OMAP343X_PADCONF_ETK_D10 … #define OMAP343X_PADCONF_ETK_D11 … #define OMAP343X_PADCONF_ETK_D12 … #define OMAP343X_PADCONF_ETK_D13 … #define OMAP343X_PADCONF_ETK_D14 … #define OMAP343X_PADCONF_ETK_D15 … /* 34xx GENERAL_WKUP register offsets */ #define OMAP34XX_CONTROL_WKUP_CTRL … #define OMAP36XX_GPIO_IO_PWRDNZ … #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) … #define OMAP343X_CONTROL_WKUP_DEBOBS0 … #define OMAP343X_CONTROL_WKUP_DEBOBS1 … #define OMAP343X_CONTROL_WKUP_DEBOBS2 … #define OMAP343X_CONTROL_WKUP_DEBOBS3 … #define OMAP343X_CONTROL_WKUP_DEBOBS4 … /* 36xx-only RTA - Retention till Access control registers and bits */ #define OMAP36XX_CONTROL_MEM_RTA_CTRL … #define OMAP36XX_RTA_DISABLE … /* 34xx D2D idle-related pins, handled by PM core */ #define OMAP3_PADCONF_SAD2D_MSTANDBY … #define OMAP3_PADCONF_SAD2D_IDLEACK … /* TI81XX CONTROL_DEVBOOT register offsets */ #define TI81XX_CONTROL_STATUS … /* TI81XX CONTROL_DEVCONF register offsets */ #define TI81XX_CONTROL_DEVICE_ID … /* OMAP4 CONTROL MODULE */ #define OMAP4_CTRL_MODULE_PAD_WKUP … #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 … #define OMAP4_CTRL_MODULE_CORE_STATUS … #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 … #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR … #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY … #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX … /* OMAP4 CONTROL_DSIPHY */ #define OMAP4_DSI2_LANEENABLE_SHIFT … #define OMAP4_DSI2_LANEENABLE_MASK … #define OMAP4_DSI1_LANEENABLE_SHIFT … #define OMAP4_DSI1_LANEENABLE_MASK … #define OMAP4_DSI1_PIPD_SHIFT … #define OMAP4_DSI1_PIPD_MASK … #define OMAP4_DSI2_PIPD_SHIFT … #define OMAP4_DSI2_PIPD_MASK … /* OMAP4 CONTROL_CAMERA_RX */ #define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT … #define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK … #define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT … #define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK … #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT … #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK … #define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT … #define OMAP4_CAMERARX_CSI22_CAMMODE_MASK … #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT … #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK … #define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT … #define OMAP4_CAMERARX_CSI21_CAMMODE_MASK … /* OMAP54XX CONTROL STATUS register */ #define OMAP5XXX_CONTROL_STATUS … #define OMAP5_DEVICETYPE_MASK … /* DRA7XX CONTROL CORE BOOTSTRAP */ #define DRA7_CTRL_CORE_BOOTSTRAP … #define DRA7_SPEEDSELECT_MASK … /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. */ /* * Control module register bit defines - these should eventually go into * their own regbits file. Some of these will be complicated, depending * on the device type (general-purpose, emulator, test, secure, bad, other) * and the security mode (secure, non-secure, don't care) */ /* CONTROL_DEVCONF0 bits */ #define OMAP2_MMCSDIO1ADPCLKISEL … #define OMAP24XX_USBSTANDBYCTRL … #define OMAP2_MCBSP2_CLKS_MASK … #define OMAP2_MCBSP1_FSR_MASK … #define OMAP2_MCBSP1_CLKR_MASK … #define OMAP2_MCBSP1_CLKS_MASK … /* CONTROL_DEVCONF1 bits */ #define OMAP243X_MMC1_ACTIVE_OVERWRITE … #define OMAP2_MMCSDIO2ADPCLKISEL … #define OMAP2_MCBSP5_CLKS_MASK … #define OMAP2_MCBSP4_CLKS_MASK … #define OMAP2_MCBSP3_CLKS_MASK … /* CONTROL_STATUS bits */ #define OMAP2_DEVICETYPE_MASK … #define OMAP2_SYSBOOT_5_MASK … #define OMAP2_SYSBOOT_4_MASK … #define OMAP2_SYSBOOT_3_MASK … #define OMAP2_SYSBOOT_2_MASK … #define OMAP2_SYSBOOT_1_MASK … #define OMAP2_SYSBOOT_0_MASK … /* CONTROL_PBIAS_LITE bits */ #define OMAP343X_PBIASLITESUPPLY_HIGH1 … #define OMAP343X_PBIASLITEVMODEERROR1 … #define OMAP343X_PBIASSPEEDCTRL1 … #define OMAP343X_PBIASLITEPWRDNZ1 … #define OMAP343X_PBIASLITEVMODE1 … #define OMAP343X_PBIASLITESUPPLY_HIGH0 … #define OMAP343X_PBIASLITEVMODEERROR0 … #define OMAP2_PBIASSPEEDCTRL0 … #define OMAP2_PBIASLITEPWRDNZ0 … #define OMAP2_PBIASLITEVMODE0 … /* CONTROL_PROG_IO1 bits */ #define OMAP3630_PRG_SDMMC1_SPEEDCTRL … /* CONTROL_IVA2_BOOTMOD bits */ #define OMAP3_IVA2_BOOTMOD_SHIFT … #define OMAP3_IVA2_BOOTMOD_MASK … #define OMAP3_IVA2_BOOTMOD_IDLE … /* CONTROL_PADCONF_X bits */ #define OMAP3_PADCONF_WAKEUPEVENT0 … #define OMAP3_PADCONF_WAKEUPENABLE0 … #define OMAP343X_SCRATCHPAD_ROM … #define OMAP343X_SCRATCHPAD … #define OMAP343X_SCRATCHPAD_ROM_OFFSET … #define OMAP343X_SCRATCHPAD_REGADDR(reg) … /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ #define AM35XX_USBOTG_VBUSP_CLK_SHIFT … #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT … #define AM35XX_VPFE_VBUSP_CLK_SHIFT … #define AM35XX_HECC_VBUSP_CLK_SHIFT … #define AM35XX_USBOTG_FCLK_SHIFT … #define AM35XX_CPGMAC_FCLK_SHIFT … #define AM35XX_VPFE_FCLK_SHIFT … /* AM35XX CONTROL_LVL_INTR_CLEAR bits */ #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR … #define AM35XX_CPGMAC_C0_RX_PULSE_CLR … #define AM35XX_CPGMAC_C0_RX_THRESH_CLR … #define AM35XX_CPGMAC_C0_TX_PULSE_CLR … #define AM35XX_USBOTGSS_INT_CLR … #define AM35XX_VPFE_CCDC_VD0_INT_CLR … #define AM35XX_VPFE_CCDC_VD1_INT_CLR … #define AM35XX_VPFE_CCDC_VD2_INT_CLR … /* AM35XX CONTROL_IP_SW_RESET bits */ #define AM35XX_USBOTGSS_SW_RST … #define AM35XX_CPGMACSS_SW_RST … #define AM35XX_VPFE_VBUSP_SW_RST … #define AM35XX_HECC_SW_RST … #define AM35XX_VPFE_PCLK_SW_RST … /* AM33XX CONTROL_STATUS register */ #define AM33XX_CONTROL_STATUS … #define AM33XX_CONTROL_SEC_CLK_CTRL … /* AM33XX CONTROL_STATUS bitfields (partial) */ #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT … #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH … #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK … /* AM33XX PWMSS Control register */ #define AM33XX_PWMSS_TBCLK_CLKCTRL … /* AM33XX PWMSS Control bitfields */ #define AM33XX_PWMSS0_TBCLKEN_SHIFT … #define AM33XX_PWMSS1_TBCLKEN_SHIFT … #define AM33XX_PWMSS2_TBCLKEN_SHIFT … /* DEV Feature register to identify AM33XX features */ #define AM33XX_DEV_FEATURE … #define AM33XX_SGX_MASK … /* Additional AM33XX/AM43XX CONTROL registers */ #define AM33XX_CONTROL_SYSCONFIG_OFFSET … #define AM33XX_CONTROL_STATUS_OFFSET … #define AM43XX_CONTROL_MPU_L2_CTRL_OFFSET … #define AM33XX_CONTROL_CORTEX_VBBLDO_CTRL_OFFSET … #define AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET … #define AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET … #define AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET … #define AM33XX_CONTROL_BANDGAP_CTRL_OFFSET … #define AM33XX_CONTROL_BANDGAP_TRIM_OFFSET … #define AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET … #define AM33XX_CONTROL_MOSC_CTRL_OFFSET … #define AM33XX_CONTROL_RCOSC_CTRL_OFFSET … #define AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET … #define AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET … #define AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET … #define AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET … #define AM33XX_CONTROL_MMU_CFG_OFFSET … #define AM33XX_CONTROL_TPTC_CFG_OFFSET … #define AM33XX_CONTROL_USB_CTRL0_OFFSET … #define AM33XX_CONTROL_USB_CTRL1_OFFSET … #define AM33XX_CONTROL_USB_WKUP_CTRL_OFFSET … #define AM43XX_CONTROL_USB_CTRL2_OFFSET … #define AM43XX_CONTROL_GMII_SEL_OFFSET … #define AM43XX_CONTROL_MPUSS_CTRL_OFFSET … #define AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET … #define AM43XX_CONTROL_PWMSS_CTRL_OFFSET … #define AM33XX_CONTROL_MREQPRIO_0_OFFSET … #define AM33XX_CONTROL_MREQPRIO_1_OFFSET … #define AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET … #define AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET … #define AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET … #define AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET … #define AM33XX_CONTROL_SMRT_CTRL_OFFSET … #define AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET … #define AM43XX_CONTROL_CQDETECT_STS_OFFSET … #define AM43XX_CONTROL_CQDETECT_STS2_OFFSET … #define AM43XX_CONTROL_VTP_CTRL_OFFSET … #define AM33XX_CONTROL_VREF_CTRL_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET … #define AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET … #define AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET … #define AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET … #define AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET … #define AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET … #define AM33XX_CONTROL_RESET_ISO_OFFSET … /* CONTROL OMAP STATUS register to identify OMAP3 features */ #define OMAP3_CONTROL_OMAP_STATUS … #define OMAP3_SGX_SHIFT … #define OMAP3_SGX_MASK … #define FEAT_SGX_FULL … #define FEAT_SGX_HALF … #define FEAT_SGX_NONE … #define OMAP3_IVA_SHIFT … #define OMAP3_IVA_MASK … #define FEAT_IVA … #define FEAT_IVA_NONE … #define OMAP3_L2CACHE_SHIFT … #define OMAP3_L2CACHE_MASK … #define FEAT_L2CACHE_NONE … #define FEAT_L2CACHE_64KB … #define FEAT_L2CACHE_128KB … #define FEAT_L2CACHE_256KB … #define OMAP3_ISP_SHIFT … #define OMAP3_ISP_MASK … #define FEAT_ISP … #define FEAT_ISP_NONE … #define OMAP3_NEON_SHIFT … #define OMAP3_NEON_MASK … #define FEAT_NEON … #define FEAT_NEON_NONE … #ifndef __ASSEMBLY__ #ifdef CONFIG_ARCH_OMAP2PLUS extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); extern u32 omap_ctrl_readl(u16 offset); extern void omap_ctrl_writeb(u8 val, u16 offset); extern void omap_ctrl_writew(u16 val, u16 offset); extern void omap_ctrl_writel(u32 val, u16 offset); extern void omap3_restore(void); extern void omap3_restore_es3(void); extern void omap3_restore_3630(void); extern u32 omap3_arm_context[128]; extern void omap3_control_save_context(void); extern void omap3_control_restore_context(void); extern void omap3_ctrl_write_boot_mode(u8 bootmode); extern void omap3630_ctrl_disable_rta(void); extern int omap3_ctrl_save_padconf(void); void omap3_ctrl_init(void); int omap2_control_base_init(void); int omap_control_init(void); #else #define omap_ctrl_readb(x) … #define omap_ctrl_readw(x) … #define omap_ctrl_readl(x) … #define omap4_ctrl_pad_readl(x) … #define omap_ctrl_writeb(x, y) … #define omap_ctrl_writew(x, y) … #define omap_ctrl_writel(x, y) … #define omap4_ctrl_pad_writel(x, y) … #endif #endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */
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