linux/drivers/staging/media/sunxi/cedrus/cedrus_h265.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Cedrus VPU driver
 *
 * Copyright (C) 2013 Jens Kuske <[email protected]>
 * Copyright (C) 2018 Paul Kocialkowski <[email protected]>
 * Copyright (C) 2018 Bootlin
 */

#include <linux/delay.h>
#include <linux/types.h>

#include <media/videobuf2-dma-contig.h>

#include "cedrus.h"
#include "cedrus_hw.h"
#include "cedrus_regs.h"

/*
 * These are the sizes for side buffers required by the hardware for storing
 * internal decoding metadata. They match the values used by the early BSP
 * implementations, that were initially exposed in libvdpau-sunxi.
 * Subsequent BSP implementations seem to double the neighbor info buffer size
 * for the H6 SoC, which may be related to 10 bit H265 support.
 */
#define CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE …
#define CEDRUS_H265_ENTRY_POINTS_BUF_SIZE …
#define CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE …

struct cedrus_h265_sram_frame_info { … } __packed;

struct cedrus_h265_sram_pred_weight { … } __packed;

static unsigned int cedrus_h265_2bit_size(unsigned int width,
					  unsigned int height)
{ … }

static enum cedrus_irq_status cedrus_h265_irq_status(struct cedrus_ctx *ctx)
{ … }

static void cedrus_h265_irq_clear(struct cedrus_ctx *ctx)
{ … }

static void cedrus_h265_irq_disable(struct cedrus_ctx *ctx)
{ … }

static void cedrus_h265_sram_write_offset(struct cedrus_dev *dev, u32 offset)
{ … }

static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, void *data,
					unsigned int size)
{ … }

static inline dma_addr_t
cedrus_h265_frame_info_mv_col_buf_addr(struct vb2_buffer *buf,
				       unsigned int field)
{ … }

static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
						unsigned int index,
						bool field_pic,
						u32 pic_order_cnt[],
						struct vb2_buffer *buf)
{ … }

static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx,
					     const struct v4l2_hevc_dpb_entry *dpb,
					     u8 num_active_dpb_entries)
{ … }

static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev,
					   const struct v4l2_hevc_dpb_entry *dpb,
					   const u8 list[],
					   u8 num_ref_idx_active,
					   u32 sram_offset)
{ … }

static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev,
					  const s8 delta_luma_weight[],
					  const s8 luma_offset[],
					  const s8 delta_chroma_weight[][2],
					  const s8 chroma_offset[][2],
					  u8 num_ref_idx_active,
					  u32 sram_luma_offset,
					  u32 sram_chroma_offset)
{ … }

static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num)
{ … }

static u32 cedrus_h265_show_bits(struct cedrus_dev *dev, int num)
{ … }

static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
					   struct cedrus_run *run)
{ … }

static int cedrus_h265_is_low_delay(struct cedrus_run *run)
{ … }

static void cedrus_h265_write_tiles(struct cedrus_ctx *ctx,
				    struct cedrus_run *run,
				    unsigned int ctb_addr_x,
				    unsigned int ctb_addr_y)
{ … }

static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
{ … }

static int cedrus_h265_start(struct cedrus_ctx *ctx)
{ … }

static void cedrus_h265_stop(struct cedrus_ctx *ctx)
{ … }

static void cedrus_h265_trigger(struct cedrus_ctx *ctx)
{ … }

static unsigned int cedrus_h265_extra_cap_size(struct cedrus_ctx *ctx,
					       struct v4l2_pix_format *pix_fmt)
{ … }

struct cedrus_dec_ops cedrus_dec_ops_h265 = …;