/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ /* * Copyright (c) 2022 MediaTek Inc. * Author: Garmin Chang <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT8188_H #define _DT_BINDINGS_CLK_MT8188_H /* TOPCKGEN */ #define CLK_TOP_AXI … #define CLK_TOP_SPM … #define CLK_TOP_SCP … #define CLK_TOP_BUS_AXIMEM … #define CLK_TOP_VPP … #define CLK_TOP_ETHDR … #define CLK_TOP_IPE … #define CLK_TOP_CAM … #define CLK_TOP_CCU … #define CLK_TOP_CCU_AHB … #define CLK_TOP_IMG … #define CLK_TOP_CAMTM … #define CLK_TOP_DSP … #define CLK_TOP_DSP1 … #define CLK_TOP_DSP2 … #define CLK_TOP_DSP3 … #define CLK_TOP_DSP4 … #define CLK_TOP_DSP5 … #define CLK_TOP_DSP6 … #define CLK_TOP_DSP7 … #define CLK_TOP_MFG_CORE_TMP … #define CLK_TOP_CAMTG … #define CLK_TOP_CAMTG2 … #define CLK_TOP_CAMTG3 … #define CLK_TOP_UART … #define CLK_TOP_SPI … #define CLK_TOP_MSDC50_0_HCLK … #define CLK_TOP_MSDC50_0 … #define CLK_TOP_MSDC30_1 … #define CLK_TOP_MSDC30_2 … #define CLK_TOP_INTDIR … #define CLK_TOP_AUD_INTBUS … #define CLK_TOP_AUDIO_H … #define CLK_TOP_PWRAP_ULPOSC … #define CLK_TOP_ATB … #define CLK_TOP_SSPM … #define CLK_TOP_DP … #define CLK_TOP_EDP … #define CLK_TOP_DPI … #define CLK_TOP_DISP_PWM0 … #define CLK_TOP_DISP_PWM1 … #define CLK_TOP_USB_TOP … #define CLK_TOP_SSUSB_XHCI … #define CLK_TOP_USB_TOP_2P … #define CLK_TOP_SSUSB_XHCI_2P … #define CLK_TOP_USB_TOP_3P … #define CLK_TOP_SSUSB_XHCI_3P … #define CLK_TOP_I2C … #define CLK_TOP_SENINF … #define CLK_TOP_SENINF1 … #define CLK_TOP_GCPU … #define CLK_TOP_VENC … #define CLK_TOP_VDEC … #define CLK_TOP_PWM … #define CLK_TOP_MCUPM … #define CLK_TOP_SPMI_P_MST … #define CLK_TOP_SPMI_M_MST … #define CLK_TOP_DVFSRC … #define CLK_TOP_TL … #define CLK_TOP_AES_MSDCFDE … #define CLK_TOP_DSI_OCC … #define CLK_TOP_WPE_VPP … #define CLK_TOP_HDCP … #define CLK_TOP_HDCP_24M … #define CLK_TOP_HDMI_APB … #define CLK_TOP_SNPS_ETH_250M … #define CLK_TOP_SNPS_ETH_62P4M_PTP … #define CLK_TOP_SNPS_ETH_50M_RMII … #define CLK_TOP_ADSP … #define CLK_TOP_AUDIO_LOCAL_BUS … #define CLK_TOP_ASM_H … #define CLK_TOP_ASM_L … #define CLK_TOP_APLL1 … #define CLK_TOP_APLL2 … #define CLK_TOP_APLL3 … #define CLK_TOP_APLL4 … #define CLK_TOP_APLL5 … #define CLK_TOP_I2SO1 … #define CLK_TOP_I2SO2 … #define CLK_TOP_I2SI1 … #define CLK_TOP_I2SI2 … #define CLK_TOP_DPTX … #define CLK_TOP_AUD_IEC … #define CLK_TOP_A1SYS_HP … #define CLK_TOP_A2SYS … #define CLK_TOP_A3SYS … #define CLK_TOP_A4SYS … #define CLK_TOP_ECC … #define CLK_TOP_SPINOR … #define CLK_TOP_ULPOSC … #define CLK_TOP_SRCK … #define CLK_TOP_MFG_CK_FAST_REF … #define CLK_TOP_MAINPLL_D3 … #define CLK_TOP_MAINPLL_D4 … #define CLK_TOP_MAINPLL_D4_D2 … #define CLK_TOP_MAINPLL_D4_D4 … #define CLK_TOP_MAINPLL_D4_D8 … #define CLK_TOP_MAINPLL_D5 … #define CLK_TOP_MAINPLL_D5_D2 … #define CLK_TOP_MAINPLL_D5_D4 … #define CLK_TOP_MAINPLL_D5_D8 … #define CLK_TOP_MAINPLL_D6 … #define CLK_TOP_MAINPLL_D6_D2 … #define CLK_TOP_MAINPLL_D6_D4 … #define CLK_TOP_MAINPLL_D6_D8 … #define CLK_TOP_MAINPLL_D7 … #define CLK_TOP_MAINPLL_D7_D2 … #define CLK_TOP_MAINPLL_D7_D4 … #define CLK_TOP_MAINPLL_D7_D8 … #define CLK_TOP_MAINPLL_D9 … #define CLK_TOP_UNIVPLL_D2 … #define CLK_TOP_UNIVPLL_D3 … #define CLK_TOP_UNIVPLL_D4 … #define CLK_TOP_UNIVPLL_D4_D2 … #define CLK_TOP_UNIVPLL_D4_D4 … #define CLK_TOP_UNIVPLL_D4_D8 … #define CLK_TOP_UNIVPLL_D5 … #define CLK_TOP_UNIVPLL_D5_D2 … #define CLK_TOP_UNIVPLL_D5_D4 … #define CLK_TOP_UNIVPLL_D5_D8 … #define CLK_TOP_UNIVPLL_D6 … #define CLK_TOP_UNIVPLL_D6_D2 … #define CLK_TOP_UNIVPLL_D6_D4 … #define CLK_TOP_UNIVPLL_D6_D8 … #define CLK_TOP_UNIVPLL_D7 … #define CLK_TOP_UNIVPLL_192M … #define CLK_TOP_UNIVPLL_192M_D4 … #define CLK_TOP_UNIVPLL_192M_D8 … #define CLK_TOP_UNIVPLL_192M_D10 … #define CLK_TOP_UNIVPLL_192M_D16 … #define CLK_TOP_UNIVPLL_192M_D32 … #define CLK_TOP_APLL1_D3 … #define CLK_TOP_APLL1_D4 … #define CLK_TOP_APLL2_D3 … #define CLK_TOP_APLL2_D4 … #define CLK_TOP_APLL3_D4 … #define CLK_TOP_APLL4_D4 … #define CLK_TOP_APLL5_D4 … #define CLK_TOP_MMPLL_D4 … #define CLK_TOP_MMPLL_D4_D2 … #define CLK_TOP_MMPLL_D5 … #define CLK_TOP_MMPLL_D5_D2 … #define CLK_TOP_MMPLL_D5_D4 … #define CLK_TOP_MMPLL_D6 … #define CLK_TOP_MMPLL_D6_D2 … #define CLK_TOP_MMPLL_D7 … #define CLK_TOP_MMPLL_D9 … #define CLK_TOP_TVDPLL1 … #define CLK_TOP_TVDPLL1_D2 … #define CLK_TOP_TVDPLL1_D4 … #define CLK_TOP_TVDPLL1_D8 … #define CLK_TOP_TVDPLL1_D16 … #define CLK_TOP_TVDPLL2 … #define CLK_TOP_TVDPLL2_D2 … #define CLK_TOP_TVDPLL2_D4 … #define CLK_TOP_TVDPLL2_D8 … #define CLK_TOP_TVDPLL2_D16 … #define CLK_TOP_MSDCPLL_D2 … #define CLK_TOP_MSDCPLL_D16 … #define CLK_TOP_ETHPLL … #define CLK_TOP_ETHPLL_D2 … #define CLK_TOP_ETHPLL_D4 … #define CLK_TOP_ETHPLL_D8 … #define CLK_TOP_ETHPLL_D10 … #define CLK_TOP_ADSPPLL_D2 … #define CLK_TOP_ADSPPLL_D4 … #define CLK_TOP_ADSPPLL_D8 … #define CLK_TOP_ULPOSC1 … #define CLK_TOP_ULPOSC1_D2 … #define CLK_TOP_ULPOSC1_D4 … #define CLK_TOP_ULPOSC1_D8 … #define CLK_TOP_ULPOSC1_D7 … #define CLK_TOP_ULPOSC1_D10 … #define CLK_TOP_ULPOSC1_D16 … #define CLK_TOP_MPHONE_SLAVE_BCK … #define CLK_TOP_PAD_FPC … #define CLK_TOP_466M_FMEM … #define CLK_TOP_PEXTP_PIPE … #define CLK_TOP_DSI_PHY … #define CLK_TOP_APLL12_CK_DIV0 … #define CLK_TOP_APLL12_CK_DIV1 … #define CLK_TOP_APLL12_CK_DIV2 … #define CLK_TOP_APLL12_CK_DIV3 … #define CLK_TOP_APLL12_CK_DIV4 … #define CLK_TOP_APLL12_CK_DIV9 … #define CLK_TOP_CFGREG_CLOCK_EN_VPP0 … #define CLK_TOP_CFGREG_CLOCK_EN_VPP1 … #define CLK_TOP_CFGREG_CLOCK_EN_VDO0 … #define CLK_TOP_CFGREG_CLOCK_EN_VDO1 … #define CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS … #define CLK_TOP_CFGREG_F26M_VPP0 … #define CLK_TOP_CFGREG_F26M_VPP1 … #define CLK_TOP_CFGREG_F26M_VDO0 … #define CLK_TOP_CFGREG_F26M_VDO1 … #define CLK_TOP_CFGREG_AUD_F26M_AUD … #define CLK_TOP_CFGREG_UNIPLL_SES … #define CLK_TOP_CFGREG_F_PCIE_PHY_REF … #define CLK_TOP_SSUSB_TOP_REF … #define CLK_TOP_SSUSB_PHY_REF … #define CLK_TOP_SSUSB_TOP_P1_REF … #define CLK_TOP_SSUSB_PHY_P1_REF … #define CLK_TOP_SSUSB_TOP_P2_REF … #define CLK_TOP_SSUSB_PHY_P2_REF … #define CLK_TOP_SSUSB_TOP_P3_REF … #define CLK_TOP_SSUSB_PHY_P3_REF … #define CLK_TOP_NR_CLK … /* INFRACFG_AO */ #define CLK_INFRA_AO_PMIC_TMR … #define CLK_INFRA_AO_PMIC_AP … #define CLK_INFRA_AO_PMIC_MD … #define CLK_INFRA_AO_PMIC_CONN … #define CLK_INFRA_AO_SEJ … #define CLK_INFRA_AO_APXGPT … #define CLK_INFRA_AO_GCE … #define CLK_INFRA_AO_GCE2 … #define CLK_INFRA_AO_THERM … #define CLK_INFRA_AO_PWM_HCLK … #define CLK_INFRA_AO_PWM1 … #define CLK_INFRA_AO_PWM2 … #define CLK_INFRA_AO_PWM3 … #define CLK_INFRA_AO_PWM4 … #define CLK_INFRA_AO_PWM … #define CLK_INFRA_AO_UART0 … #define CLK_INFRA_AO_UART1 … #define CLK_INFRA_AO_UART2 … #define CLK_INFRA_AO_UART3 … #define CLK_INFRA_AO_UART4 … #define CLK_INFRA_AO_GCE_26M … #define CLK_INFRA_AO_CQ_DMA_FPC … #define CLK_INFRA_AO_UART5 … #define CLK_INFRA_AO_HDMI_26M … #define CLK_INFRA_AO_SPI0 … #define CLK_INFRA_AO_MSDC0 … #define CLK_INFRA_AO_MSDC1 … #define CLK_INFRA_AO_MSDC2 … #define CLK_INFRA_AO_MSDC0_SRC … #define CLK_INFRA_AO_DVFSRC … #define CLK_INFRA_AO_TRNG … #define CLK_INFRA_AO_AUXADC … #define CLK_INFRA_AO_CPUM … #define CLK_INFRA_AO_HDMI_32K … #define CLK_INFRA_AO_CEC_66M_HCLK … #define CLK_INFRA_AO_PCIE_TL_26M … #define CLK_INFRA_AO_MSDC1_SRC … #define CLK_INFRA_AO_CEC_66M_BCLK … #define CLK_INFRA_AO_PCIE_TL_96M … #define CLK_INFRA_AO_DEVICE_APC … #define CLK_INFRA_AO_ECC_66M_HCLK … #define CLK_INFRA_AO_DEBUGSYS … #define CLK_INFRA_AO_AUDIO … #define CLK_INFRA_AO_PCIE_TL_32K … #define CLK_INFRA_AO_DBG_TRACE … #define CLK_INFRA_AO_DRAMC_F26M … #define CLK_INFRA_AO_IRTX … #define CLK_INFRA_AO_DISP_PWM … #define CLK_INFRA_AO_CLDMA_BCLK … #define CLK_INFRA_AO_AUDIO_26M_BCLK … #define CLK_INFRA_AO_SPI1 … #define CLK_INFRA_AO_SPI2 … #define CLK_INFRA_AO_SPI3 … #define CLK_INFRA_AO_FSSPM … #define CLK_INFRA_AO_SSPM_BUS_HCLK … #define CLK_INFRA_AO_APDMA_BCLK … #define CLK_INFRA_AO_SPI4 … #define CLK_INFRA_AO_SPI5 … #define CLK_INFRA_AO_CQ_DMA … #define CLK_INFRA_AO_MSDC0_SELF … #define CLK_INFRA_AO_MSDC1_SELF … #define CLK_INFRA_AO_MSDC2_SELF … #define CLK_INFRA_AO_I2S_DMA … #define CLK_INFRA_AO_AP_MSDC0 … #define CLK_INFRA_AO_MD_MSDC0 … #define CLK_INFRA_AO_MSDC30_2 … #define CLK_INFRA_AO_GCPU … #define CLK_INFRA_AO_PCIE_PERI_26M … #define CLK_INFRA_AO_GCPU_66M_BCLK … #define CLK_INFRA_AO_GCPU_133M_BCLK … #define CLK_INFRA_AO_DISP_PWM1 … #define CLK_INFRA_AO_FBIST2FPC … #define CLK_INFRA_AO_DEVICE_APC_SYNC … #define CLK_INFRA_AO_PCIE_P1_PERI_26M … #define CLK_INFRA_AO_133M_MCLK_CK … #define CLK_INFRA_AO_66M_MCLK_CK … #define CLK_INFRA_AO_PCIE_PL_P_250M_P0 … #define CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P … #define CLK_INFRA_AO_NR_CLK … /* APMIXEDSYS */ #define CLK_APMIXED_ETHPLL … #define CLK_APMIXED_MSDCPLL … #define CLK_APMIXED_TVDPLL1 … #define CLK_APMIXED_TVDPLL2 … #define CLK_APMIXED_MMPLL … #define CLK_APMIXED_MAINPLL … #define CLK_APMIXED_IMGPLL … #define CLK_APMIXED_UNIVPLL … #define CLK_APMIXED_ADSPPLL … #define CLK_APMIXED_APLL1 … #define CLK_APMIXED_APLL2 … #define CLK_APMIXED_APLL3 … #define CLK_APMIXED_APLL4 … #define CLK_APMIXED_APLL5 … #define CLK_APMIXED_MFGPLL … #define CLK_APMIXED_PLL_SSUSB26M_EN … #define CLK_APMIXED_NR_CLK … /* AUDIODSP */ #define CLK_AUDIODSP_AUDIO26M … #define CLK_AUDIODSP_NR_CLK … /* PERICFG_AO */ #define CLK_PERI_AO_ETHERNET … #define CLK_PERI_AO_ETHERNET_BUS … #define CLK_PERI_AO_FLASHIF_BUS … #define CLK_PERI_AO_FLASHIF_26M … #define CLK_PERI_AO_FLASHIFLASHCK … #define CLK_PERI_AO_SSUSB_2P_BUS … #define CLK_PERI_AO_SSUSB_2P_XHCI … #define CLK_PERI_AO_SSUSB_3P_BUS … #define CLK_PERI_AO_SSUSB_3P_XHCI … #define CLK_PERI_AO_SSUSB_BUS … #define CLK_PERI_AO_SSUSB_XHCI … #define CLK_PERI_AO_ETHERNET_MAC … #define CLK_PERI_AO_PCIE_P0_FMEM … #define CLK_PERI_AO_NR_CLK … /* IMP_IIC_WRAP_C */ #define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0 … #define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2 … #define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3 … #define CLK_IMP_IIC_WRAP_C_NR_CLK … /* IMP_IIC_WRAP_W */ #define CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1 … #define CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4 … #define CLK_IMP_IIC_WRAP_W_NR_CLK … /* IMP_IIC_WRAP_EN */ #define CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5 … #define CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6 … #define CLK_IMP_IIC_WRAP_EN_NR_CLK … /* MFGCFG */ #define CLK_MFGCFG_BG3D … #define CLK_MFGCFG_NR_CLK … /* VPPSYS0 */ #define CLK_VPP0_MDP_FG … #define CLK_VPP0_STITCH … #define CLK_VPP0_PADDING … #define CLK_VPP0_MDP_TCC … #define CLK_VPP0_WARP0_ASYNC_TX … #define CLK_VPP0_WARP1_ASYNC_TX … #define CLK_VPP0_MUTEX … #define CLK_VPP02VPP1_RELAY … #define CLK_VPP0_VPP12VPP0_ASYNC … #define CLK_VPP0_MMSYSRAM_TOP … #define CLK_VPP0_MDP_AAL … #define CLK_VPP0_MDP_RSZ … #define CLK_VPP0_SMI_COMMON_MMSRAM … #define CLK_VPP0_GALS_VDO0_LARB0_MMSRAM … #define CLK_VPP0_GALS_VDO0_LARB1_MMSRAM … #define CLK_VPP0_GALS_VENCSYS_MMSRAM … #define CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM … #define CLK_VPP0_GALS_INFRA_MMSRAM … #define CLK_VPP0_GALS_CAMSYS_MMSRAM … #define CLK_VPP0_GALS_VPP1_LARB5_MMSRAM … #define CLK_VPP0_GALS_VPP1_LARB6_MMSRAM … #define CLK_VPP0_SMI_REORDER_MMSRAM … #define CLK_VPP0_SMI_IOMMU … #define CLK_VPP0_GALS_IMGSYS_CAMSYS … #define CLK_VPP0_MDP_RDMA … #define CLK_VPP0_MDP_WROT … #define CLK_VPP0_GALS_EMI0_EMI1 … #define CLK_VPP0_SMI_SUB_COMMON_REORDER … #define CLK_VPP0_SMI_RSI … #define CLK_VPP0_SMI_COMMON_LARB4 … #define CLK_VPP0_GALS_VDEC_VDEC_CORE1 … #define CLK_VPP0_GALS_VPP1_WPESYS … #define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 … #define CLK_VPP0_FAKE_ENG … #define CLK_VPP0_MDP_HDR … #define CLK_VPP0_MDP_TDSHP … #define CLK_VPP0_MDP_COLOR … #define CLK_VPP0_MDP_OVL … #define CLK_VPP0_DSIP_RDMA … #define CLK_VPP0_DISP_WDMA … #define CLK_VPP0_MDP_HMS … #define CLK_VPP0_WARP0_RELAY … #define CLK_VPP0_WARP0_ASYNC … #define CLK_VPP0_WARP1_RELAY … #define CLK_VPP0_WARP1_ASYNC … #define CLK_VPP0_NR_CLK … /* WPESYS */ #define CLK_WPE_TOP_WPE_VPP0 … #define CLK_WPE_TOP_SMI_LARB7 … #define CLK_WPE_TOP_WPESYS_EVENT_TX … #define CLK_WPE_TOP_SMI_LARB7_PCLK_EN … #define CLK_WPE_TOP_NR_CLK … /* WPESYS_VPP0 */ #define CLK_WPE_VPP0_VECI … #define CLK_WPE_VPP0_VEC2I … #define CLK_WPE_VPP0_VEC3I … #define CLK_WPE_VPP0_WPEO … #define CLK_WPE_VPP0_MSKO … #define CLK_WPE_VPP0_VGEN … #define CLK_WPE_VPP0_EXT … #define CLK_WPE_VPP0_VFC … #define CLK_WPE_VPP0_CACH0_TOP … #define CLK_WPE_VPP0_CACH0_DMA … #define CLK_WPE_VPP0_CACH1_TOP … #define CLK_WPE_VPP0_CACH1_DMA … #define CLK_WPE_VPP0_CACH2_TOP … #define CLK_WPE_VPP0_CACH2_DMA … #define CLK_WPE_VPP0_CACH3_TOP … #define CLK_WPE_VPP0_CACH3_DMA … #define CLK_WPE_VPP0_PSP … #define CLK_WPE_VPP0_PSP2 … #define CLK_WPE_VPP0_SYNC … #define CLK_WPE_VPP0_C24 … #define CLK_WPE_VPP0_MDP_CROP … #define CLK_WPE_VPP0_ISP_CROP … #define CLK_WPE_VPP0_TOP … #define CLK_WPE_VPP0_NR_CLK … /* VPPSYS1 */ #define CLK_VPP1_SVPP1_MDP_OVL … #define CLK_VPP1_SVPP1_MDP_TCC … #define CLK_VPP1_SVPP1_MDP_WROT … #define CLK_VPP1_SVPP1_VPP_PAD … #define CLK_VPP1_SVPP2_MDP_WROT … #define CLK_VPP1_SVPP2_VPP_PAD … #define CLK_VPP1_SVPP3_MDP_WROT … #define CLK_VPP1_SVPP3_VPP_PAD … #define CLK_VPP1_SVPP1_MDP_RDMA … #define CLK_VPP1_SVPP1_MDP_FG … #define CLK_VPP1_SVPP2_MDP_RDMA … #define CLK_VPP1_SVPP2_MDP_FG … #define CLK_VPP1_SVPP3_MDP_RDMA … #define CLK_VPP1_SVPP3_MDP_FG … #define CLK_VPP1_VPP_SPLIT … #define CLK_VPP1_SVPP2_VDO0_DL_RELAY … #define CLK_VPP1_SVPP1_MDP_RSZ … #define CLK_VPP1_SVPP1_MDP_TDSHP … #define CLK_VPP1_SVPP1_MDP_COLOR … #define CLK_VPP1_SVPP3_VDO1_DL_RELAY … #define CLK_VPP1_SVPP2_MDP_RSZ … #define CLK_VPP1_SVPP2_VPP_MERGE … #define CLK_VPP1_SVPP2_MDP_TDSHP … #define CLK_VPP1_SVPP2_MDP_COLOR … #define CLK_VPP1_SVPP3_MDP_RSZ … #define CLK_VPP1_SVPP3_VPP_MERGE … #define CLK_VPP1_SVPP3_MDP_TDSHP … #define CLK_VPP1_SVPP3_MDP_COLOR … #define CLK_VPP1_GALS5 … #define CLK_VPP1_GALS6 … #define CLK_VPP1_LARB5 … #define CLK_VPP1_LARB6 … #define CLK_VPP1_SVPP1_MDP_HDR … #define CLK_VPP1_SVPP1_MDP_AAL … #define CLK_VPP1_SVPP2_MDP_HDR … #define CLK_VPP1_SVPP2_MDP_AAL … #define CLK_VPP1_SVPP3_MDP_HDR … #define CLK_VPP1_SVPP3_MDP_AAL … #define CLK_VPP1_DISP_MUTEX … #define CLK_VPP1_SVPP2_VDO1_DL_RELAY … #define CLK_VPP1_SVPP3_VDO0_DL_RELAY … #define CLK_VPP1_VPP0_DL_ASYNC … #define CLK_VPP1_VPP0_DL1_RELAY … #define CLK_VPP1_LARB5_FAKE_ENG … #define CLK_VPP1_LARB6_FAKE_ENG … #define CLK_VPP1_HDMI_META … #define CLK_VPP1_VPP_SPLIT_HDMI … #define CLK_VPP1_DGI_IN … #define CLK_VPP1_DGI_OUT … #define CLK_VPP1_VPP_SPLIT_DGI … #define CLK_VPP1_DL_CON_OCC … #define CLK_VPP1_VPP_SPLIT_26M … #define CLK_VPP1_NR_CLK … /* IMGSYS */ #define CLK_IMGSYS_MAIN_LARB9 … #define CLK_IMGSYS_MAIN_TRAW0 … #define CLK_IMGSYS_MAIN_TRAW1 … #define CLK_IMGSYS_MAIN_VCORE_GALS … #define CLK_IMGSYS_MAIN_DIP0 … #define CLK_IMGSYS_MAIN_WPE0 … #define CLK_IMGSYS_MAIN_IPE … #define CLK_IMGSYS_MAIN_WPE1 … #define CLK_IMGSYS_MAIN_WPE2 … #define CLK_IMGSYS_MAIN_GALS … #define CLK_IMGSYS_MAIN_NR_CLK … /* IMGSYS1_DIP_TOP */ #define CLK_IMGSYS1_DIP_TOP_LARB10 … #define CLK_IMGSYS1_DIP_TOP_DIP_TOP … #define CLK_IMGSYS1_DIP_TOP_NR_CLK … /* IMGSYS1_DIP_NR */ #define CLK_IMGSYS1_DIP_NR_LARB15 … #define CLK_IMGSYS1_DIP_NR_DIP_NR … #define CLK_IMGSYS1_DIP_NR_NR_CLK … /* IMGSYS_WPE1 */ #define CLK_IMGSYS_WPE1_LARB11 … #define CLK_IMGSYS_WPE1 … #define CLK_IMGSYS_WPE1_NR_CLK … /* IPESYS */ #define CLK_IPE_DPE … #define CLK_IPE_FDVT … #define CLK_IPE_ME … #define CLK_IPESYS_TOP … #define CLK_IPE_SMI_LARB12 … #define CLK_IPE_NR_CLK … /* IMGSYS_WPE2 */ #define CLK_IMGSYS_WPE2_LARB11 … #define CLK_IMGSYS_WPE2 … #define CLK_IMGSYS_WPE2_NR_CLK … /* IMGSYS_WPE3 */ #define CLK_IMGSYS_WPE3_LARB11 … #define CLK_IMGSYS_WPE3 … #define CLK_IMGSYS_WPE3_NR_CLK … /* CAMSYS */ #define CLK_CAM_MAIN_LARB13 … #define CLK_CAM_MAIN_LARB14 … #define CLK_CAM_MAIN_CAM … #define CLK_CAM_MAIN_CAM_SUBA … #define CLK_CAM_MAIN_CAM_SUBB … #define CLK_CAM_MAIN_CAMTG … #define CLK_CAM_MAIN_SENINF … #define CLK_CAM_MAIN_GCAMSVA … #define CLK_CAM_MAIN_GCAMSVB … #define CLK_CAM_MAIN_GCAMSVC … #define CLK_CAM_MAIN_GCAMSVD … #define CLK_CAM_MAIN_GCAMSVE … #define CLK_CAM_MAIN_GCAMSVF … #define CLK_CAM_MAIN_GCAMSVG … #define CLK_CAM_MAIN_GCAMSVH … #define CLK_CAM_MAIN_GCAMSVI … #define CLK_CAM_MAIN_GCAMSVJ … #define CLK_CAM_MAIN_CAMSV_TOP … #define CLK_CAM_MAIN_CAMSV_CQ_A … #define CLK_CAM_MAIN_CAMSV_CQ_B … #define CLK_CAM_MAIN_CAMSV_CQ_C … #define CLK_CAM_MAIN_FAKE_ENG … #define CLK_CAM_MAIN_CAM2MM0_GALS … #define CLK_CAM_MAIN_CAM2MM1_GALS … #define CLK_CAM_MAIN_CAM2SYS_GALS … #define CLK_CAM_MAIN_NR_CLK … /* CAMSYS_RAWA */ #define CLK_CAM_RAWA_LARBX … #define CLK_CAM_RAWA_CAM … #define CLK_CAM_RAWA_CAMTG … #define CLK_CAM_RAWA_NR_CLK … /* CAMSYS_YUVA */ #define CLK_CAM_YUVA_LARBX … #define CLK_CAM_YUVA_CAM … #define CLK_CAM_YUVA_CAMTG … #define CLK_CAM_YUVA_NR_CLK … /* CAMSYS_RAWB */ #define CLK_CAM_RAWB_LARBX … #define CLK_CAM_RAWB_CAM … #define CLK_CAM_RAWB_CAMTG … #define CLK_CAM_RAWB_NR_CLK … /* CAMSYS_YUVB */ #define CLK_CAM_YUVB_LARBX … #define CLK_CAM_YUVB_CAM … #define CLK_CAM_YUVB_CAMTG … #define CLK_CAM_YUVB_NR_CLK … /* CCUSYS */ #define CLK_CCU_LARB27 … #define CLK_CCU_AHB … #define CLK_CCU_CCU0 … #define CLK_CCU_NR_CLK … /* VDECSYS_SOC */ #define CLK_VDEC1_SOC_LARB1 … #define CLK_VDEC1_SOC_LAT … #define CLK_VDEC1_SOC_LAT_ACTIVE … #define CLK_VDEC1_SOC_LAT_ENG … #define CLK_VDEC1_SOC_VDEC … #define CLK_VDEC1_SOC_VDEC_ACTIVE … #define CLK_VDEC1_SOC_VDEC_ENG … #define CLK_VDEC1_NR_CLK … /* VDECSYS */ #define CLK_VDEC2_LARB1 … #define CLK_VDEC2_LAT … #define CLK_VDEC2_VDEC … #define CLK_VDEC2_VDEC_ACTIVE … #define CLK_VDEC2_VDEC_ENG … #define CLK_VDEC2_NR_CLK … /* VENCSYS */ #define CLK_VENC1_LARB … #define CLK_VENC1_VENC … #define CLK_VENC1_JPGENC … #define CLK_VENC1_JPGDEC … #define CLK_VENC1_JPGDEC_C1 … #define CLK_VENC1_GALS … #define CLK_VENC1_GALS_SRAM … #define CLK_VENC1_NR_CLK … /* VDOSYS0 */ #define CLK_VDO0_DISP_OVL0 … #define CLK_VDO0_FAKE_ENG0 … #define CLK_VDO0_DISP_CCORR0 … #define CLK_VDO0_DISP_MUTEX0 … #define CLK_VDO0_DISP_GAMMA0 … #define CLK_VDO0_DISP_DITHER0 … #define CLK_VDO0_DISP_WDMA0 … #define CLK_VDO0_DISP_RDMA0 … #define CLK_VDO0_DSI0 … #define CLK_VDO0_DSI1 … #define CLK_VDO0_DSC_WRAP0 … #define CLK_VDO0_VPP_MERGE0 … #define CLK_VDO0_DP_INTF0 … #define CLK_VDO0_DISP_AAL0 … #define CLK_VDO0_INLINEROT0 … #define CLK_VDO0_APB_BUS … #define CLK_VDO0_DISP_COLOR0 … #define CLK_VDO0_MDP_WROT0 … #define CLK_VDO0_DISP_RSZ0 … #define CLK_VDO0_DISP_POSTMASK0 … #define CLK_VDO0_FAKE_ENG1 … #define CLK_VDO0_DL_ASYNC2 … #define CLK_VDO0_DL_RELAY3 … #define CLK_VDO0_DL_RELAY4 … #define CLK_VDO0_SMI_GALS … #define CLK_VDO0_SMI_COMMON … #define CLK_VDO0_SMI_EMI … #define CLK_VDO0_SMI_IOMMU … #define CLK_VDO0_SMI_LARB … #define CLK_VDO0_SMI_RSI … #define CLK_VDO0_DSI0_DSI … #define CLK_VDO0_DSI1_DSI … #define CLK_VDO0_DP_INTF0_DP_INTF … #define CLK_VDO0_NR_CLK … /* VDOSYS1 */ #define CLK_VDO1_SMI_LARB2 … #define CLK_VDO1_SMI_LARB3 … #define CLK_VDO1_GALS … #define CLK_VDO1_FAKE_ENG0 … #define CLK_VDO1_FAKE_ENG1 … #define CLK_VDO1_MDP_RDMA0 … #define CLK_VDO1_MDP_RDMA1 … #define CLK_VDO1_MDP_RDMA2 … #define CLK_VDO1_MDP_RDMA3 … #define CLK_VDO1_VPP_MERGE0 … #define CLK_VDO1_VPP_MERGE1 … #define CLK_VDO1_VPP_MERGE2 … #define CLK_VDO1_VPP_MERGE3 … #define CLK_VDO1_VPP_MERGE4 … #define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC … #define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC … #define CLK_VDO1_DISP_MUTEX … #define CLK_VDO1_MDP_RDMA4 … #define CLK_VDO1_MDP_RDMA5 … #define CLK_VDO1_MDP_RDMA6 … #define CLK_VDO1_MDP_RDMA7 … #define CLK_VDO1_DP_INTF0_MMCK … #define CLK_VDO1_DPI0_MM … #define CLK_VDO1_DPI1_MM … #define CLK_VDO1_MERGE0_DL_ASYNC … #define CLK_VDO1_MERGE1_DL_ASYNC … #define CLK_VDO1_MERGE2_DL_ASYNC … #define CLK_VDO1_MERGE3_DL_ASYNC … #define CLK_VDO1_MERGE4_DL_ASYNC … #define CLK_VDO1_DSC_VDO1_DL_ASYNC … #define CLK_VDO1_MERGE_VDO1_DL_ASYNC … #define CLK_VDO1_PADDING0 … #define CLK_VDO1_PADDING1 … #define CLK_VDO1_PADDING2 … #define CLK_VDO1_PADDING3 … #define CLK_VDO1_PADDING4 … #define CLK_VDO1_PADDING5 … #define CLK_VDO1_PADDING6 … #define CLK_VDO1_PADDING7 … #define CLK_VDO1_DISP_RSZ0 … #define CLK_VDO1_DISP_RSZ1 … #define CLK_VDO1_DISP_RSZ2 … #define CLK_VDO1_DISP_RSZ3 … #define CLK_VDO1_HDR_VDO_FE0 … #define CLK_VDO1_HDR_GFX_FE0 … #define CLK_VDO1_HDR_VDO_BE … #define CLK_VDO1_HDR_VDO_FE1 … #define CLK_VDO1_HDR_GFX_FE1 … #define CLK_VDO1_DISP_MIXER … #define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC … #define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC … #define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC … #define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC … #define CLK_VDO1_HDR_VDO_BE_DL_ASYNC … #define CLK_VDO1_DPI0 … #define CLK_VDO1_DISP_MONITOR_DPI0 … #define CLK_VDO1_DPI1 … #define CLK_VDO1_DISP_MONITOR_DPI1 … #define CLK_VDO1_DPINTF … #define CLK_VDO1_DISP_MONITOR_DPINTF … #define CLK_VDO1_26M_SLOW … #define CLK_VDO1_NR_CLK … #endif /* _DT_BINDINGS_CLK_MT8188_H */
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