/* SPDX-License-Identifier: GPL-2.0+ */ /* * Driver for Realtek PCI-Express card reader * * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. * * Author: * Wei WANG ([email protected]) * Micky Ching ([email protected]) */ #ifndef __REALTEK_RTSX_XD_H #define __REALTEK_RTSX_XD_H #define XD_DELAY_WRITE /* Error Codes */ #define XD_NO_ERROR … #define XD_NO_MEMORY … #define XD_PRG_ERROR … #define XD_NO_CARD … #define XD_READ_FAIL … #define XD_ERASE_FAIL … #define XD_WRITE_FAIL … #define XD_ECC_ERROR … #define XD_TO_ERROR … /* XD Commands */ #define READ1_1 … #define READ1_2 … #define READ2 … #define READ_ID … #define RESET … #define PAGE_PRG_1 … #define PAGE_PRG_2 … #define BLK_ERASE_1 … #define BLK_ERASE_2 … #define READ_STS … #define READ_XD_ID … #define COPY_BACK_512 … #define COPY_BACK_2K … #define READ1_1_2 … #define READ1_1_3 … #define CHG_DAT_OUT_1 … #define RDM_DAT_OUT_1 … #define CHG_DAT_OUT_2 … #define RDM_DAT_OUT_2 … #define CHG_DAT_OUT_2 … #define CHG_DAT_IN_1 … #define CACHE_PRG … /* Redundant Area Related */ #define XD_EXTRA_SIZE … #define XD_2K_EXTRA_SIZE … #define NOT_WRITE_PROTECTED … #define READY_STATE … #define PROGRAM_ERROR … #define PROGRAM_ERROR_N_1 … #define INTERNAL_READY … #define READY_FLAG … #define XD_8M_X8_512 … #define XD_16M_X8_512 … #define XD_32M_X8_512 … #define XD_64M_X8_512 … #define XD_128M_X8_512 … #define XD_256M_X8_512 … #define XD_128M_X8_2048 … #define XD_256M_X8_2048 … #define XD_512M_X8 … #define XD_128M_X16_2048 … #define XD_4M_X8_512_1 … #define XD_4M_X8_512_2 … #define XD_1G_X8_512 … #define XD_2G_X8_512 … #define XD_ID_CODE … #define VENDOR_BLOCK … #define CIS_BLOCK … #define BLK_NOT_FOUND … #define NO_NEW_BLK … #define PAGE_CORRECTABLE … #define PAGE_NOTCORRECTABLE … #define NO_OFFSET … #define WITH_OFFSET … #define SECT_PER_PAGE … #define XD_ADDR_MODE_2C … #define ZONE0_BAD_BLOCK … #define NOT_ZONE0_BAD_BLOCK … #define XD_RW_ADDR … #define XD_ERASE_ADDR … #define XD_PAGE_512(xd_card) … #define XD_SET_BAD_NEWBLK(xd_card) … #define XD_CLR_BAD_NEWBLK(xd_card) … #define XD_CHK_BAD_NEWBLK(xd_card) … #define XD_SET_BAD_OLDBLK(xd_card) … #define XD_CLR_BAD_OLDBLK(xd_card) … #define XD_CHK_BAD_OLDBLK(xd_card) … #define XD_SET_MBR_FAIL(xd_card) … #define XD_CLR_MBR_FAIL(xd_card) … #define XD_CHK_MBR_FAIL(xd_card) … #define XD_SET_ECC_FLD_ERR(xd_card) … #define XD_CLR_ECC_FLD_ERR(xd_card) … #define XD_CHK_ECC_FLD_ERR(xd_card) … #define XD_SET_4MB(xd_card) … #define XD_CLR_4MB(xd_card) … #define XD_CHK_4MB(xd_card) … #define XD_SET_ECC_ERR(xd_card) … #define XD_CLR_ECC_ERR(xd_card) … #define XD_CHK_ECC_ERR(xd_card) … #define PAGE_STATUS … #define BLOCK_STATUS … #define BLOCK_ADDR1_L … #define BLOCK_ADDR1_H … #define BLOCK_ADDR2_L … #define BLOCK_ADDR2_H … #define RESERVED0 … #define RESERVED1 … #define RESERVED2 … #define RESERVED3 … #define PARITY … #define CIS0_0 … #define CIS0_1 … #define CIS0_2 … #define CIS0_3 … #define CIS0_4 … #define CIS0_5 … #define CIS0_6 … #define CIS0_7 … #define CIS0_8 … #define CIS0_9 … #define CIS1_0 … #define CIS1_1 … #define CIS1_2 … #define CIS1_3 … #define CIS1_4 … #define CIS1_5 … #define CIS1_6 … #define CIS1_7 … #define CIS1_8 … #define CIS1_9 … int reset_xd_card(struct rtsx_chip *chip); #ifdef XD_DELAY_WRITE int xd_delay_write(struct rtsx_chip *chip); #endif int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt); void xd_free_l2p_tbl(struct rtsx_chip *chip); void xd_cleanup_work(struct rtsx_chip *chip); int xd_power_off_card3v3(struct rtsx_chip *chip); int release_xd_card(struct rtsx_chip *chip); #endif /* __REALTEK_RTSX_XD_H */
Codebase Browser
linux