linux/include/dt-bindings/reset/mt8188-resets.h

/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
/*
 * Copyright (c) 2022 MediaTek Inc.
 * Author: Runyang Chen <[email protected]>
 */

#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188
#define _DT_BINDINGS_RESET_CONTROLLER_MT8188

#define MT8188_TOPRGU_CONN_MCU_SW_RST
#define MT8188_TOPRGU_INFRA_GRST_SW_RST
#define MT8188_TOPRGU_IPU0_SW_RST
#define MT8188_TOPRGU_IPU1_SW_RST
#define MT8188_TOPRGU_IPU2_SW_RST
#define MT8188_TOPRGU_AUD_ASRC_SW_RST
#define MT8188_TOPRGU_INFRA_SW_RST
#define MT8188_TOPRGU_MMSYS_SW_RST
#define MT8188_TOPRGU_MFG_SW_RST
#define MT8188_TOPRGU_VENC_SW_RST
#define MT8188_TOPRGU_VDEC_SW_RST
#define MT8188_TOPRGU_CAM_VCORE_SW_RST
#define MT8188_TOPRGU_SCP_SW_RST
#define MT8188_TOPRGU_APMIXEDSYS_SW_RST
#define MT8188_TOPRGU_AUDIO_SW_RST
#define MT8188_TOPRGU_CAMSYS_SW_RST
#define MT8188_TOPRGU_MJC_SW_RST
#define MT8188_TOPRGU_PERI_SW_RST
#define MT8188_TOPRGU_PERI_AO_SW_RST
#define MT8188_TOPRGU_PCIE_SW_RST
#define MT8188_TOPRGU_ADSPSYS_SW_RST
#define MT8188_TOPRGU_DPTX_SW_RST
#define MT8188_TOPRGU_SPMI_MST_SW_RST

#define MT8188_TOPRGU_SW_RST_NUM

/* INFRA resets */
#define MT8188_INFRA_RST1_THERMAL_MCU_RST
#define MT8188_INFRA_RST1_THERMAL_CTRL_RST
#define MT8188_INFRA_RST3_PTP_CTRL_RST

#define MT8188_VDO0_RST_DISP_OVL0
#define MT8188_VDO0_RST_FAKE_ENG0
#define MT8188_VDO0_RST_DISP_CCORR0
#define MT8188_VDO0_RST_DISP_MUTEX0
#define MT8188_VDO0_RST_DISP_GAMMA0
#define MT8188_VDO0_RST_DISP_DITHER0
#define MT8188_VDO0_RST_DISP_WDMA0
#define MT8188_VDO0_RST_DISP_RDMA0
#define MT8188_VDO0_RST_DSI0
#define MT8188_VDO0_RST_DSI1
#define MT8188_VDO0_RST_DSC_WRAP0
#define MT8188_VDO0_RST_VPP_MERGE0
#define MT8188_VDO0_RST_DP_INTF0
#define MT8188_VDO0_RST_DISP_AAL0
#define MT8188_VDO0_RST_INLINEROT0
#define MT8188_VDO0_RST_APB_BUS
#define MT8188_VDO0_RST_DISP_COLOR0
#define MT8188_VDO0_RST_MDP_WROT0
#define MT8188_VDO0_RST_DISP_RSZ0

#define MT8188_VDO1_RST_SMI_LARB2
#define MT8188_VDO1_RST_SMI_LARB3
#define MT8188_VDO1_RST_GALS
#define MT8188_VDO1_RST_FAKE_ENG0
#define MT8188_VDO1_RST_FAKE_ENG1
#define MT8188_VDO1_RST_MDP_RDMA0
#define MT8188_VDO1_RST_MDP_RDMA1
#define MT8188_VDO1_RST_MDP_RDMA2
#define MT8188_VDO1_RST_MDP_RDMA3
#define MT8188_VDO1_RST_VPP_MERGE0
#define MT8188_VDO1_RST_VPP_MERGE1
#define MT8188_VDO1_RST_VPP_MERGE2
#define MT8188_VDO1_RST_VPP_MERGE3
#define MT8188_VDO1_RST_VPP_MERGE4
#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC
#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC
#define MT8188_VDO1_RST_DISP_MUTEX
#define MT8188_VDO1_RST_MDP_RDMA4
#define MT8188_VDO1_RST_MDP_RDMA5
#define MT8188_VDO1_RST_MDP_RDMA6
#define MT8188_VDO1_RST_MDP_RDMA7
#define MT8188_VDO1_RST_DP_INTF1_MMCK
#define MT8188_VDO1_RST_DPI0_MM_CK
#define MT8188_VDO1_RST_DPI1_MM_CK
#define MT8188_VDO1_RST_MERGE0_DL_ASYNC
#define MT8188_VDO1_RST_MERGE1_DL_ASYNC
#define MT8188_VDO1_RST_MERGE2_DL_ASYNC
#define MT8188_VDO1_RST_MERGE3_DL_ASYNC
#define MT8188_VDO1_RST_MERGE4_DL_ASYNC
#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC
#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC
#define MT8188_VDO1_RST_PADDING0
#define MT8188_VDO1_RST_PADDING1
#define MT8188_VDO1_RST_PADDING2
#define MT8188_VDO1_RST_PADDING3
#define MT8188_VDO1_RST_PADDING4
#define MT8188_VDO1_RST_PADDING5
#define MT8188_VDO1_RST_PADDING6
#define MT8188_VDO1_RST_PADDING7
#define MT8188_VDO1_RST_DISP_RSZ0
#define MT8188_VDO1_RST_DISP_RSZ1
#define MT8188_VDO1_RST_DISP_RSZ2
#define MT8188_VDO1_RST_DISP_RSZ3
#define MT8188_VDO1_RST_HDR_VDO_FE0
#define MT8188_VDO1_RST_HDR_GFX_FE0
#define MT8188_VDO1_RST_HDR_VDO_BE
#define MT8188_VDO1_RST_HDR_VDO_FE1
#define MT8188_VDO1_RST_HDR_GFX_FE1
#define MT8188_VDO1_RST_DISP_MIXER
#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC
#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC
#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC
#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC
#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC

#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */