/* SPDX-License-Identifier: GPL-2.0 */ #ifndef DDK750_DISPLAY_H__ #define DDK750_DISPLAY_H__ /* * panel path select * 80000[29:28] */ #define PNL_2_OFFSET … #define PNL_2_MASK … #define PNL_2_USAGE … #define PNL_2_PRI … #define PNL_2_SEC … /* * primary timing & plane enable bit * 1: 80000[8] & 80000[2] on * 0: both off */ #define PRI_TP_OFFSET … #define PRI_TP_MASK … #define PRI_TP_USAGE … #define PRI_TP_ON … #define PRI_TP_OFF … /* * panel sequency status * 80000[27:24] */ #define PNL_SEQ_OFFSET … #define PNL_SEQ_MASK … #define PNL_SEQ_USAGE … #define PNL_SEQ_ON … #define PNL_SEQ_OFF … /* * dual digital output * 80000[19] */ #define DUAL_TFT_OFFSET … #define DUAL_TFT_MASK … #define DUAL_TFT_USAGE … #define DUAL_TFT_ON … #define DUAL_TFT_OFF … /* * secondary timing & plane enable bit * 1:80200[8] & 80200[2] on * 0: both off */ #define SEC_TP_OFFSET … #define SEC_TP_MASK … #define SEC_TP_USAGE … #define SEC_TP_ON … #define SEC_TP_OFF … /* * crt path select * 80200[19:18] */ #define CRT_2_OFFSET … #define CRT_2_MASK … #define CRT_2_USAGE … #define CRT_2_PRI … #define CRT_2_SEC … /* * DAC affect both DVI and DSUB * 4[20] */ #define DAC_OFFSET … #define DAC_MASK … #define DAC_USAGE … #define DAC_ON … #define DAC_OFF … /* * DPMS only affect D-SUB head * 0[31:30] */ #define DPMS_OFFSET … #define DPMS_MASK … #define DPMS_USAGE … #define DPMS_OFF … #define DPMS_ON … /* * LCD1 means panel path TFT1 & panel path DVI (so enable DAC) * CRT means crt path DSUB */ enum disp_output { … }; void ddk750_set_logical_disp_out(enum disp_output output); #endif
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