/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2021 MediaTek Inc. * Author: Chun-Jie Chen <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT8192_H #define _DT_BINDINGS_CLK_MT8192_H /* TOPCKGEN */ #define CLK_TOP_AXI_SEL … #define CLK_TOP_SPM_SEL … #define CLK_TOP_SCP_SEL … #define CLK_TOP_BUS_AXIMEM_SEL … #define CLK_TOP_DISP_SEL … #define CLK_TOP_MDP_SEL … #define CLK_TOP_IMG1_SEL … #define CLK_TOP_IMG2_SEL … #define CLK_TOP_IPE_SEL … #define CLK_TOP_DPE_SEL … #define CLK_TOP_CAM_SEL … #define CLK_TOP_CCU_SEL … #define CLK_TOP_DSP7_SEL … #define CLK_TOP_MFG_REF_SEL … #define CLK_TOP_MFG_PLL_SEL … #define CLK_TOP_CAMTG_SEL … #define CLK_TOP_CAMTG2_SEL … #define CLK_TOP_CAMTG3_SEL … #define CLK_TOP_CAMTG4_SEL … #define CLK_TOP_CAMTG5_SEL … #define CLK_TOP_CAMTG6_SEL … #define CLK_TOP_UART_SEL … #define CLK_TOP_SPI_SEL … #define CLK_TOP_MSDC50_0_H_SEL … #define CLK_TOP_MSDC50_0_SEL … #define CLK_TOP_MSDC30_1_SEL … #define CLK_TOP_MSDC30_2_SEL … #define CLK_TOP_AUDIO_SEL … #define CLK_TOP_AUD_INTBUS_SEL … #define CLK_TOP_PWRAP_ULPOSC_SEL … #define CLK_TOP_ATB_SEL … #define CLK_TOP_DPI_SEL … #define CLK_TOP_SCAM_SEL … #define CLK_TOP_DISP_PWM_SEL … #define CLK_TOP_USB_TOP_SEL … #define CLK_TOP_SSUSB_XHCI_SEL … #define CLK_TOP_I2C_SEL … #define CLK_TOP_SENINF_SEL … #define CLK_TOP_SENINF1_SEL … #define CLK_TOP_SENINF2_SEL … #define CLK_TOP_SENINF3_SEL … #define CLK_TOP_TL_SEL … #define CLK_TOP_DXCC_SEL … #define CLK_TOP_AUD_ENGEN1_SEL … #define CLK_TOP_AUD_ENGEN2_SEL … #define CLK_TOP_AES_UFSFDE_SEL … #define CLK_TOP_UFS_SEL … #define CLK_TOP_AUD_1_SEL … #define CLK_TOP_AUD_2_SEL … #define CLK_TOP_ADSP_SEL … #define CLK_TOP_DPMAIF_MAIN_SEL … #define CLK_TOP_VENC_SEL … #define CLK_TOP_VDEC_SEL … #define CLK_TOP_CAMTM_SEL … #define CLK_TOP_PWM_SEL … #define CLK_TOP_AUDIO_H_SEL … #define CLK_TOP_SPMI_MST_SEL … #define CLK_TOP_AES_MSDCFDE_SEL … #define CLK_TOP_SFLASH_SEL … #define CLK_TOP_APLL_I2S0_M_SEL … #define CLK_TOP_APLL_I2S1_M_SEL … #define CLK_TOP_APLL_I2S2_M_SEL … #define CLK_TOP_APLL_I2S3_M_SEL … #define CLK_TOP_APLL_I2S4_M_SEL … #define CLK_TOP_APLL_I2S5_M_SEL … #define CLK_TOP_APLL_I2S6_M_SEL … #define CLK_TOP_APLL_I2S7_M_SEL … #define CLK_TOP_APLL_I2S8_M_SEL … #define CLK_TOP_APLL_I2S9_M_SEL … #define CLK_TOP_MAINPLL_D3 … #define CLK_TOP_MAINPLL_D4 … #define CLK_TOP_MAINPLL_D4_D2 … #define CLK_TOP_MAINPLL_D4_D4 … #define CLK_TOP_MAINPLL_D4_D8 … #define CLK_TOP_MAINPLL_D4_D16 … #define CLK_TOP_MAINPLL_D5 … #define CLK_TOP_MAINPLL_D5_D2 … #define CLK_TOP_MAINPLL_D5_D4 … #define CLK_TOP_MAINPLL_D5_D8 … #define CLK_TOP_MAINPLL_D6 … #define CLK_TOP_MAINPLL_D6_D2 … #define CLK_TOP_MAINPLL_D6_D4 … #define CLK_TOP_MAINPLL_D7 … #define CLK_TOP_MAINPLL_D7_D2 … #define CLK_TOP_MAINPLL_D7_D4 … #define CLK_TOP_MAINPLL_D7_D8 … #define CLK_TOP_UNIVPLL_D3 … #define CLK_TOP_UNIVPLL_D4 … #define CLK_TOP_UNIVPLL_D4_D2 … #define CLK_TOP_UNIVPLL_D4_D4 … #define CLK_TOP_UNIVPLL_D4_D8 … #define CLK_TOP_UNIVPLL_D5 … #define CLK_TOP_UNIVPLL_D5_D2 … #define CLK_TOP_UNIVPLL_D5_D4 … #define CLK_TOP_UNIVPLL_D5_D8 … #define CLK_TOP_UNIVPLL_D6 … #define CLK_TOP_UNIVPLL_D6_D2 … #define CLK_TOP_UNIVPLL_D6_D4 … #define CLK_TOP_UNIVPLL_D6_D8 … #define CLK_TOP_UNIVPLL_D6_D16 … #define CLK_TOP_UNIVPLL_D7 … #define CLK_TOP_APLL1 … #define CLK_TOP_APLL1_D2 … #define CLK_TOP_APLL1_D4 … #define CLK_TOP_APLL1_D8 … #define CLK_TOP_APLL2 … #define CLK_TOP_APLL2_D2 … #define CLK_TOP_APLL2_D4 … #define CLK_TOP_APLL2_D8 … #define CLK_TOP_MMPLL_D4 … #define CLK_TOP_MMPLL_D4_D2 … #define CLK_TOP_MMPLL_D5 … #define CLK_TOP_MMPLL_D5_D2 … #define CLK_TOP_MMPLL_D6 … #define CLK_TOP_MMPLL_D6_D2 … #define CLK_TOP_MMPLL_D7 … #define CLK_TOP_MMPLL_D9 … #define CLK_TOP_APUPLL … #define CLK_TOP_NPUPLL … #define CLK_TOP_TVDPLL … #define CLK_TOP_TVDPLL_D2 … #define CLK_TOP_TVDPLL_D4 … #define CLK_TOP_TVDPLL_D8 … #define CLK_TOP_TVDPLL_D16 … #define CLK_TOP_MSDCPLL … #define CLK_TOP_MSDCPLL_D2 … #define CLK_TOP_MSDCPLL_D4 … #define CLK_TOP_ULPOSC … #define CLK_TOP_OSC_D2 … #define CLK_TOP_OSC_D4 … #define CLK_TOP_OSC_D8 … #define CLK_TOP_OSC_D10 … #define CLK_TOP_OSC_D16 … #define CLK_TOP_OSC_D20 … #define CLK_TOP_CSW_F26M_D2 … #define CLK_TOP_ADSPPLL … #define CLK_TOP_UNIVPLL_192M … #define CLK_TOP_UNIVPLL_192M_D2 … #define CLK_TOP_UNIVPLL_192M_D4 … #define CLK_TOP_UNIVPLL_192M_D8 … #define CLK_TOP_UNIVPLL_192M_D16 … #define CLK_TOP_UNIVPLL_192M_D32 … #define CLK_TOP_APLL12_DIV0 … #define CLK_TOP_APLL12_DIV1 … #define CLK_TOP_APLL12_DIV2 … #define CLK_TOP_APLL12_DIV3 … #define CLK_TOP_APLL12_DIV4 … #define CLK_TOP_APLL12_DIVB … #define CLK_TOP_APLL12_DIV5 … #define CLK_TOP_APLL12_DIV6 … #define CLK_TOP_APLL12_DIV7 … #define CLK_TOP_APLL12_DIV8 … #define CLK_TOP_APLL12_DIV9 … #define CLK_TOP_SSUSB_TOP_REF … #define CLK_TOP_SSUSB_PHY_REF … #define CLK_TOP_NR_CLK … /* INFRACFG */ #define CLK_INFRA_PMIC_TMR … #define CLK_INFRA_PMIC_AP … #define CLK_INFRA_PMIC_MD … #define CLK_INFRA_PMIC_CONN … #define CLK_INFRA_SCPSYS … #define CLK_INFRA_SEJ … #define CLK_INFRA_APXGPT … #define CLK_INFRA_GCE … #define CLK_INFRA_GCE2 … #define CLK_INFRA_THERM … #define CLK_INFRA_I2C0 … #define CLK_INFRA_AP_DMA_PSEUDO … #define CLK_INFRA_I2C2 … #define CLK_INFRA_I2C3 … #define CLK_INFRA_PWM_H … #define CLK_INFRA_PWM1 … #define CLK_INFRA_PWM2 … #define CLK_INFRA_PWM3 … #define CLK_INFRA_PWM4 … #define CLK_INFRA_PWM … #define CLK_INFRA_UART0 … #define CLK_INFRA_UART1 … #define CLK_INFRA_UART2 … #define CLK_INFRA_UART3 … #define CLK_INFRA_GCE_26M … #define CLK_INFRA_CQ_DMA_FPC … #define CLK_INFRA_BTIF … #define CLK_INFRA_SPI0 … #define CLK_INFRA_MSDC0 … #define CLK_INFRA_MSDC1 … #define CLK_INFRA_MSDC2 … #define CLK_INFRA_MSDC0_SRC … #define CLK_INFRA_GCPU … #define CLK_INFRA_TRNG … #define CLK_INFRA_AUXADC … #define CLK_INFRA_CPUM … #define CLK_INFRA_CCIF1_AP … #define CLK_INFRA_CCIF1_MD … #define CLK_INFRA_AUXADC_MD … #define CLK_INFRA_PCIE_TL_26M … #define CLK_INFRA_MSDC1_SRC … #define CLK_INFRA_MSDC2_SRC … #define CLK_INFRA_PCIE_TL_96M … #define CLK_INFRA_PCIE_PL_P_250M … #define CLK_INFRA_DEVICE_APC … #define CLK_INFRA_CCIF_AP … #define CLK_INFRA_DEBUGSYS … #define CLK_INFRA_AUDIO … #define CLK_INFRA_CCIF_MD … #define CLK_INFRA_DXCC_SEC_CORE … #define CLK_INFRA_DXCC_AO … #define CLK_INFRA_DBG_TRACE … #define CLK_INFRA_DEVMPU_B … #define CLK_INFRA_DRAMC_F26M … #define CLK_INFRA_IRTX … #define CLK_INFRA_SSUSB … #define CLK_INFRA_DISP_PWM … #define CLK_INFRA_CLDMA_B … #define CLK_INFRA_AUDIO_26M_B … #define CLK_INFRA_MODEM_TEMP_SHARE … #define CLK_INFRA_SPI1 … #define CLK_INFRA_I2C4 … #define CLK_INFRA_SPI2 … #define CLK_INFRA_SPI3 … #define CLK_INFRA_UNIPRO_SYS … #define CLK_INFRA_UNIPRO_TICK … #define CLK_INFRA_UFS_MP_SAP_B … #define CLK_INFRA_MD32_B … #define CLK_INFRA_UNIPRO_MBIST … #define CLK_INFRA_I2C5 … #define CLK_INFRA_I2C5_ARBITER … #define CLK_INFRA_I2C5_IMM … #define CLK_INFRA_I2C1_ARBITER … #define CLK_INFRA_I2C1_IMM … #define CLK_INFRA_I2C2_ARBITER … #define CLK_INFRA_I2C2_IMM … #define CLK_INFRA_SPI4 … #define CLK_INFRA_SPI5 … #define CLK_INFRA_CQ_DMA … #define CLK_INFRA_UFS … #define CLK_INFRA_AES_UFSFDE … #define CLK_INFRA_UFS_TICK … #define CLK_INFRA_SSUSB_XHCI … #define CLK_INFRA_MSDC0_SELF … #define CLK_INFRA_MSDC1_SELF … #define CLK_INFRA_MSDC2_SELF … #define CLK_INFRA_UFS_AXI … #define CLK_INFRA_I2C6 … #define CLK_INFRA_AP_MSDC0 … #define CLK_INFRA_MD_MSDC0 … #define CLK_INFRA_CCIF5_AP … #define CLK_INFRA_CCIF5_MD … #define CLK_INFRA_PCIE_TOP_H_133M … #define CLK_INFRA_FLASHIF_TOP_H_133M … #define CLK_INFRA_PCIE_PERI_26M … #define CLK_INFRA_CCIF2_AP … #define CLK_INFRA_CCIF2_MD … #define CLK_INFRA_CCIF3_AP … #define CLK_INFRA_CCIF3_MD … #define CLK_INFRA_SEJ_F13M … #define CLK_INFRA_AES … #define CLK_INFRA_I2C7 … #define CLK_INFRA_I2C8 … #define CLK_INFRA_FBIST2FPC … #define CLK_INFRA_DEVICE_APC_SYNC … #define CLK_INFRA_DPMAIF_MAIN … #define CLK_INFRA_PCIE_TL_32K … #define CLK_INFRA_CCIF4_AP … #define CLK_INFRA_CCIF4_MD … #define CLK_INFRA_SPI6 … #define CLK_INFRA_SPI7 … #define CLK_INFRA_133M … #define CLK_INFRA_66M … #define CLK_INFRA_66M_PERI_BUS … #define CLK_INFRA_FREE_DCM_133M … #define CLK_INFRA_FREE_DCM_66M … #define CLK_INFRA_PERI_BUS_DCM_133M … #define CLK_INFRA_PERI_BUS_DCM_66M … #define CLK_INFRA_FLASHIF_PERI_26M … #define CLK_INFRA_FLASHIF_SFLASH … #define CLK_INFRA_AP_DMA … #define CLK_INFRA_NR_CLK … /* PERICFG */ #define CLK_PERI_PERIAXI … #define CLK_PERI_NR_CLK … /* APMIXEDSYS */ #define CLK_APMIXED_MAINPLL … #define CLK_APMIXED_UNIVPLL … #define CLK_APMIXED_USBPLL … #define CLK_APMIXED_MSDCPLL … #define CLK_APMIXED_MMPLL … #define CLK_APMIXED_ADSPPLL … #define CLK_APMIXED_MFGPLL … #define CLK_APMIXED_TVDPLL … #define CLK_APMIXED_APLL1 … #define CLK_APMIXED_APLL2 … #define CLK_APMIXED_MIPID26M … #define CLK_APMIXED_NR_CLK … /* SCP_ADSP */ #define CLK_SCP_ADSP_AUDIODSP … #define CLK_SCP_ADSP_NR_CLK … /* IMP_IIC_WRAP_C */ #define CLK_IMP_IIC_WRAP_C_I2C10 … #define CLK_IMP_IIC_WRAP_C_I2C11 … #define CLK_IMP_IIC_WRAP_C_I2C12 … #define CLK_IMP_IIC_WRAP_C_I2C13 … #define CLK_IMP_IIC_WRAP_C_NR_CLK … /* AUDSYS */ #define CLK_AUD_AFE … #define CLK_AUD_22M … #define CLK_AUD_24M … #define CLK_AUD_APLL2_TUNER … #define CLK_AUD_APLL_TUNER … #define CLK_AUD_TDM … #define CLK_AUD_ADC … #define CLK_AUD_DAC … #define CLK_AUD_DAC_PREDIS … #define CLK_AUD_TML … #define CLK_AUD_NLE … #define CLK_AUD_I2S1_B … #define CLK_AUD_I2S2_B … #define CLK_AUD_I2S3_B … #define CLK_AUD_I2S4_B … #define CLK_AUD_CONNSYS_I2S_ASRC … #define CLK_AUD_GENERAL1_ASRC … #define CLK_AUD_GENERAL2_ASRC … #define CLK_AUD_DAC_HIRES … #define CLK_AUD_ADC_HIRES … #define CLK_AUD_ADC_HIRES_TML … #define CLK_AUD_ADDA6_ADC … #define CLK_AUD_ADDA6_ADC_HIRES … #define CLK_AUD_3RD_DAC … #define CLK_AUD_3RD_DAC_PREDIS … #define CLK_AUD_3RD_DAC_TML … #define CLK_AUD_3RD_DAC_HIRES … #define CLK_AUD_I2S5_B … #define CLK_AUD_I2S6_B … #define CLK_AUD_I2S7_B … #define CLK_AUD_I2S8_B … #define CLK_AUD_I2S9_B … #define CLK_AUD_NR_CLK … /* IMP_IIC_WRAP_E */ #define CLK_IMP_IIC_WRAP_E_I2C3 … #define CLK_IMP_IIC_WRAP_E_NR_CLK … /* IMP_IIC_WRAP_S */ #define CLK_IMP_IIC_WRAP_S_I2C7 … #define CLK_IMP_IIC_WRAP_S_I2C8 … #define CLK_IMP_IIC_WRAP_S_I2C9 … #define CLK_IMP_IIC_WRAP_S_NR_CLK … /* IMP_IIC_WRAP_WS */ #define CLK_IMP_IIC_WRAP_WS_I2C1 … #define CLK_IMP_IIC_WRAP_WS_I2C2 … #define CLK_IMP_IIC_WRAP_WS_I2C4 … #define CLK_IMP_IIC_WRAP_WS_NR_CLK … /* IMP_IIC_WRAP_W */ #define CLK_IMP_IIC_WRAP_W_I2C5 … #define CLK_IMP_IIC_WRAP_W_NR_CLK … /* IMP_IIC_WRAP_N */ #define CLK_IMP_IIC_WRAP_N_I2C0 … #define CLK_IMP_IIC_WRAP_N_I2C6 … #define CLK_IMP_IIC_WRAP_N_NR_CLK … /* MSDC_TOP */ #define CLK_MSDC_TOP_AES_0P … #define CLK_MSDC_TOP_SRC_0P … #define CLK_MSDC_TOP_SRC_1P … #define CLK_MSDC_TOP_SRC_2P … #define CLK_MSDC_TOP_P_MSDC0 … #define CLK_MSDC_TOP_P_MSDC1 … #define CLK_MSDC_TOP_P_MSDC2 … #define CLK_MSDC_TOP_P_CFG … #define CLK_MSDC_TOP_AXI … #define CLK_MSDC_TOP_H_MST_0P … #define CLK_MSDC_TOP_H_MST_1P … #define CLK_MSDC_TOP_H_MST_2P … #define CLK_MSDC_TOP_MEM_OFF_DLY_26M … #define CLK_MSDC_TOP_32K … #define CLK_MSDC_TOP_AHB2AXI_BRG_AXI … #define CLK_MSDC_TOP_NR_CLK … /* MSDC */ #define CLK_MSDC_AXI_WRAP … #define CLK_MSDC_NR_CLK … /* MFGCFG */ #define CLK_MFG_BG3D … #define CLK_MFG_NR_CLK … /* MMSYS */ #define CLK_MM_DISP_MUTEX0 … #define CLK_MM_DISP_CONFIG … #define CLK_MM_DISP_OVL0 … #define CLK_MM_DISP_RDMA0 … #define CLK_MM_DISP_OVL0_2L … #define CLK_MM_DISP_WDMA0 … #define CLK_MM_DISP_UFBC_WDMA0 … #define CLK_MM_DISP_RSZ0 … #define CLK_MM_DISP_AAL0 … #define CLK_MM_DISP_CCORR0 … #define CLK_MM_DISP_DITHER0 … #define CLK_MM_SMI_INFRA … #define CLK_MM_DISP_GAMMA0 … #define CLK_MM_DISP_POSTMASK0 … #define CLK_MM_DISP_DSC_WRAP0 … #define CLK_MM_DSI0 … #define CLK_MM_DISP_COLOR0 … #define CLK_MM_SMI_COMMON … #define CLK_MM_DISP_FAKE_ENG0 … #define CLK_MM_DISP_FAKE_ENG1 … #define CLK_MM_MDP_TDSHP4 … #define CLK_MM_MDP_RSZ4 … #define CLK_MM_MDP_AAL4 … #define CLK_MM_MDP_HDR4 … #define CLK_MM_MDP_RDMA4 … #define CLK_MM_MDP_COLOR4 … #define CLK_MM_DISP_Y2R0 … #define CLK_MM_SMI_GALS … #define CLK_MM_DISP_OVL2_2L … #define CLK_MM_DISP_RDMA4 … #define CLK_MM_DISP_DPI0 … #define CLK_MM_SMI_IOMMU … #define CLK_MM_DSI_DSI0 … #define CLK_MM_DPI_DPI0 … #define CLK_MM_26MHZ … #define CLK_MM_32KHZ … #define CLK_MM_NR_CLK … /* IMGSYS */ #define CLK_IMG_LARB9 … #define CLK_IMG_LARB10 … #define CLK_IMG_DIP … #define CLK_IMG_GALS … #define CLK_IMG_NR_CLK … /* IMGSYS2 */ #define CLK_IMG2_LARB11 … #define CLK_IMG2_LARB12 … #define CLK_IMG2_MFB … #define CLK_IMG2_WPE … #define CLK_IMG2_MSS … #define CLK_IMG2_GALS … #define CLK_IMG2_NR_CLK … /* VDECSYS_SOC */ #define CLK_VDEC_SOC_LARB1 … #define CLK_VDEC_SOC_LAT … #define CLK_VDEC_SOC_LAT_ACTIVE … #define CLK_VDEC_SOC_VDEC … #define CLK_VDEC_SOC_VDEC_ACTIVE … #define CLK_VDEC_SOC_NR_CLK … /* VDECSYS */ #define CLK_VDEC_LARB1 … #define CLK_VDEC_LAT … #define CLK_VDEC_LAT_ACTIVE … #define CLK_VDEC_VDEC … #define CLK_VDEC_ACTIVE … #define CLK_VDEC_NR_CLK … /* VENCSYS */ #define CLK_VENC_SET0_LARB … #define CLK_VENC_SET1_VENC … #define CLK_VENC_SET2_JPGENC … #define CLK_VENC_SET5_GALS … #define CLK_VENC_NR_CLK … /* CAMSYS */ #define CLK_CAM_LARB13 … #define CLK_CAM_DFP_VAD … #define CLK_CAM_LARB14 … #define CLK_CAM_CAM … #define CLK_CAM_CAMTG … #define CLK_CAM_SENINF … #define CLK_CAM_CAMSV0 … #define CLK_CAM_CAMSV1 … #define CLK_CAM_CAMSV2 … #define CLK_CAM_CAMSV3 … #define CLK_CAM_CCU0 … #define CLK_CAM_CCU1 … #define CLK_CAM_MRAW0 … #define CLK_CAM_FAKE_ENG … #define CLK_CAM_CCU_GALS … #define CLK_CAM_CAM2MM_GALS … #define CLK_CAM_NR_CLK … /* CAMSYS_RAWA */ #define CLK_CAM_RAWA_LARBX … #define CLK_CAM_RAWA_CAM … #define CLK_CAM_RAWA_CAMTG … #define CLK_CAM_RAWA_NR_CLK … /* CAMSYS_RAWB */ #define CLK_CAM_RAWB_LARBX … #define CLK_CAM_RAWB_CAM … #define CLK_CAM_RAWB_CAMTG … #define CLK_CAM_RAWB_NR_CLK … /* CAMSYS_RAWC */ #define CLK_CAM_RAWC_LARBX … #define CLK_CAM_RAWC_CAM … #define CLK_CAM_RAWC_CAMTG … #define CLK_CAM_RAWC_NR_CLK … /* IPESYS */ #define CLK_IPE_LARB19 … #define CLK_IPE_LARB20 … #define CLK_IPE_SMI_SUBCOM … #define CLK_IPE_FD … #define CLK_IPE_FE … #define CLK_IPE_RSC … #define CLK_IPE_DPE … #define CLK_IPE_GALS … #define CLK_IPE_NR_CLK … /* MDPSYS */ #define CLK_MDP_RDMA0 … #define CLK_MDP_TDSHP0 … #define CLK_MDP_IMG_DL_ASYNC0 … #define CLK_MDP_IMG_DL_ASYNC1 … #define CLK_MDP_RDMA1 … #define CLK_MDP_TDSHP1 … #define CLK_MDP_SMI0 … #define CLK_MDP_APB_BUS … #define CLK_MDP_WROT0 … #define CLK_MDP_RSZ0 … #define CLK_MDP_HDR0 … #define CLK_MDP_MUTEX0 … #define CLK_MDP_WROT1 … #define CLK_MDP_RSZ1 … #define CLK_MDP_HDR1 … #define CLK_MDP_FAKE_ENG0 … #define CLK_MDP_AAL0 … #define CLK_MDP_AAL1 … #define CLK_MDP_COLOR0 … #define CLK_MDP_COLOR1 … #define CLK_MDP_IMG_DL_RELAY0_ASYNC0 … #define CLK_MDP_IMG_DL_RELAY1_ASYNC1 … #define CLK_MDP_NR_CLK … #endif /* _DT_BINDINGS_CLK_MT8192_H */
Codebase Browser
linux