clk-mt8192.c | Explore in Territory

// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"

#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/reset/mt8192-resets.h>

static DEFINE_SPINLOCK(mt8192_clk_lock);

static const struct mtk_fixed_clk top_fixed_clks[] = …;

static const struct mtk_fixed_factor top_divs[] = …;

static const char * const axi_parents[] = …;

static const char * const spm_parents[] = …;

static const char * const scp_parents[] = …;

static const char * const bus_aximem_parents[] = …;

static const char * const disp_parents[] = …;

static const char * const mdp_parents[] = …;

static const char * const img_parents[] = …;

static const char * const ipe_parents[] = …;

static const char * const dpe_parents[] = …;

static const char * const cam_parents[] = …;

static const char * const ccu_parents[] = …;

static const char * const dsp7_parents[] = …;

static const char * const mfg_ref_parents[] = …;

static const char * const mfg_pll_parents[] = …;

static const char * const camtg_parents[] = …;

static const char * const uart_parents[] = …;

static const char * const spi_parents[] = …;

static const char * const msdc50_0_h_parents[] = …;

static const char * const msdc50_0_parents[] = …;

static const char * const msdc30_parents[] = …;

static const char * const audio_parents[] = …;

static const char * const aud_intbus_parents[] = …;

static const char * const pwrap_ulposc_parents[] = …;

static const char * const atb_parents[] = …;

static const char * const dpi_parents[] = …;

static const char * const scam_parents[] = …;

static const char * const disp_pwm_parents[] = …;

static const char * const usb_top_parents[] = …;

static const char * const ssusb_xhci_parents[] = …;

static const char * const i2c_parents[] = …;

static const char * const seninf_parents[] = …;

static const char * const tl_parents[] = …;

static const char * const dxcc_parents[] = …;

static const char * const aud_engen1_parents[] = …;

static const char * const aud_engen2_parents[] = …;

static const char * const aes_ufsfde_parents[] = …;

static const char * const ufs_parents[] = …;

static const char * const aud_1_parents[] = …;

static const char * const aud_2_parents[] = …;

static const char * const adsp_parents[] = …;

static const char * const dpmaif_main_parents[] = …;

static const char * const venc_parents[] = …;

static const char * const vdec_parents[] = …;

static const char * const camtm_parents[] = …;

static const char * const pwm_parents[] = …;

static const char * const audio_h_parents[] = …;

static const char * const spmi_mst_parents[] = …;

static const char * const aes_msdcfde_parents[] = …;

static const char * const sflash_parents[] = …;

static const char * const apll_i2s_m_parents[] = …;

/*
 * CRITICAL CLOCK:
 * axi_sel is the main bus clock of whole SOC.
 * spm_sel is the clock of the always-on co-processor.
 * bus_aximem_sel is clock of the bus that access emi.
 */
static const struct mtk_mux top_mtk_muxes[] = …;

static struct mtk_composite top_muxes[] = …;

static const struct mtk_gate_regs infra0_cg_regs = …;

static const struct mtk_gate_regs infra1_cg_regs = …;

static const struct mtk_gate_regs infra2_cg_regs = …;

static const struct mtk_gate_regs infra3_cg_regs = …;

static const struct mtk_gate_regs infra4_cg_regs = …;

static const struct mtk_gate_regs infra5_cg_regs = …;

#define GATE_INFRA0(_id, _name, _parent, _shift) …

#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) …

#define GATE_INFRA1(_id, _name, _parent, _shift) …

#define GATE_INFRA2(_id, _name, _parent, _shift) …

#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) …

#define GATE_INFRA3(_id, _name, _parent, _shift) …

#define GATE_INFRA4(_id, _name, _parent, _shift) …

#define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag) …

#define GATE_INFRA5(_id, _name, _parent, _shift) …

/*
 * CRITICAL CLOCK:
 * infra_133m and infra_66m are main peripheral bus clocks of SOC.
 * infra_device_apc and infra_device_apc_sync are for device access permission control module.
 */
static const struct mtk_gate infra_clks[] = …;

static const struct mtk_gate_regs peri_cg_regs = …;

#define GATE_PERI(_id, _name, _parent, _shift) …

static const struct mtk_gate peri_clks[] = …;

static const struct mtk_gate_regs top_cg_regs = …;

#define GATE_TOP(_id, _name, _parent, _shift) …

static const struct mtk_gate top_clks[] = …;

static u16 infra_ao_rst_ofs[] = …;

static u16 infra_ao_idx_map[] = …;

static const struct mtk_clk_rst_desc clk_rst_desc = …;

/* Register mux notifier for MFG mux */
static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
{ … }

static const struct mtk_clk_desc infra_desc = …;

static const struct mtk_clk_desc peri_desc = …;

static const struct mtk_clk_desc topck_desc = …;

static const struct of_device_id of_match_clk_mt8192[] = …;
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192);

static struct platform_driver clk_mt8192_drv = …;
module_platform_driver(…) …;

MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;
linux/drivers/clk/mediatek/clk-mt8192.c
