linux/drivers/clk/mediatek/clk-mt8192-apmixedsys.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2021 MediaTek Inc.
 *               Chun-Jie Chen <[email protected]>
 * Copyright (c) 2023 Collabora Ltd.
 *               AngeloGioacchino Del Regno <[email protected]>
 */

#include <dt-bindings/clock/mt8192-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-fhctl.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"
#include "clk-pllfh.h"

static const struct mtk_gate_regs apmixed_cg_regs = …;

#define GATE_APMIXED(_id, _name, _parent, _shift) …

static const struct mtk_gate apmixed_clks[] = …;

#define MT8192_PLL_FMAX …
#define MT8192_PLL_FMIN …
#define MT8192_INTEGER_BITS …

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,		\
			_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,	\
			_tuner_reg, _tuner_en_reg, _tuner_en_bit,	\
			_pcw_reg, _pcw_shift, _pcw_chg_reg,		\
			_en_reg, _pll_en_bit) …

#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,		\
			_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,	\
			_tuner_reg, _tuner_en_reg, _tuner_en_bit,	\
			_pcw_reg, _pcw_shift) …

static const struct mtk_pll_data plls[] = …;

enum fh_pll_id { … };

#define FH(_pllid, _fhid, _offset) …

static struct mtk_pllfh_data pllfhs[] = …;

static const struct of_device_id of_match_clk_mt8192_apmixed[] = …;
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_apmixed);

static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
{ … }

static void clk_mt8192_apmixed_remove(struct platform_device *pdev)
{ … }

static struct platform_driver clk_mt8192_apmixed_drv = …;
module_platform_driver(…) …;
MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;